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AM5K2E04: DDR3 configuration: Impedance Control Register 1 (ZQnCR1)

Lennart Siekmann
Prodigy 160 points
Part Number: AM5K2E04


Hello,

Dealing with the configuration of the DDR3 interface on the TI AM5K2E04 we are facing some questions concerning the configuration of driver strength and termination values.

The K2_DDR3_Register_Calc Excel spreadsheet offers some settings for the driver strength and termination of the DDR3 bus(ses), namely

- DDR_TERM        --> configuration of the RAM's termination
- SDRAM_DRIVE --> configuration of the RAM's driver strength
- PHY Data ZO --> configuration of the memory controller's driver strength for the Data busses
- PHY ACCC ZO --> configuration of the memory controller's driver strength for address/command/control/clock
- PHY_ODT     --> configuration of the memory controller's on die termination

Manipulation of these parameters do have impact on the registers ZQ0CR1, ZQ1CR1, ZQ2CR1.
Comments available inside the spreadsheet show the following mapping:
ZQ0CR1 --> Address/Control/Command/Clock
ZQ1CR1 --> Data 0 to Data 3
ZQ2CR1 --> Data 4 to Data 7 and ECC

Referencing the Keystone II Architecture DDR3 Memory Controller User's Guide (spruhn7c) the following information is available:

Impedance Control Register 1 (ZQnCR1)
ZPROG[7:4] = On-die termination divide select. Available values: 0x2, 0x5, 0x8
ZPROG[3:0] = Output impedance divide select. Available values: 0xB, 0xD

Unfortunately I can't find any explanation of the "n" in ZQnCR1, except for its range 0...3; merging the information from the spreadsheet and the user's guide the following mapping seems to apply:

n = 0 --> Address/Control/Command/Clock
n = 1 --> Data 0 to Data 3
n = 2 --> Data 4 to Data 7 and ECC
n = 3 --> ??

with bit[3:0] configuring the output impedance and bit [7:4] controlling the termination. This leads to the following questions:

  1. Do we have to take ZQ3CR1 into account while optimizing our board specific driver and termination settings?
  2. The bits [7:4] of ZQ0CR1 seem to offer the possibility to configure an on-die termination for address/command/clock signals, which are terminated by discrete external resistors.
    Are these bits generally "don't care", or do they have any impact on the behavior of the DDR3 interface?
  3. The spreadsheet does not offer the possibility to change the parameter PHY_ODT, which should manipulate bit[7:4] of ZQ1CR1 and ZQ2CR1 - but why?
  4. Did we miss any documentation that provides more information, especially on the aforementioned registers?

Thanks, best regards

Lennart

  • 0
    TI__Mastermind 46460 points

    Lennart,

    The Keystone II Architecture DDR3 Memory Controller User's Guide (spruhn7c) is the definitive source for detailed register bitfield explanation.

    You list out the below impedance controls:

    • DDR_TERM        --> configuration of the RAM's termination
    • SDRAM_DRIVE --> configuration of the RAM's driver strength
    • PHY Data ZO --> configuration of the memory controller's driver strength for the Data busses
    • PHY ACCC ZO --> configuration of the memory controller's driver strength for address/command/control/clock
    • PHY_ODT     --> configuration of the memory controller's on die termination

    The allowable values for these bitfields are shown in the drop-down menus on the 'Design Parameters' tab of the REG_CALC worksheet.  An explanation of these source and termination impedances are shown in section 6.5.2 in DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C).

    1.  Even though the PHY address decode logic implies that there is a ZQ3CRx set of registers, these have no effect.  There are only 3 DDR macro IP blocks implemented in this device and they have the association as seen in the REG_CALC spreadsheet.

    2.  The PHY ODT value is only active in the macro during reads (input mode).  Since the ACCC macro is only ever in output mode, the PHY ODT is not active and this setting has no effect.

    3.  The spreadsheet only allows for PHY_ODT = 60 ohms as shown in Figure 15 in DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1C).  The other possible values supported by the PHY as shown in Table 4-61 of Keystone II Architecture DDR3 Memory Controller User's Guide (spruhn7c) are not recommended for use with the supported SDRAM topologies.

    4.  See above.

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 160 points

    Thanks for the clarification, Tom!

    Best regards

    Lennart