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TDA2E: DDR3 DQS Schematic Review

JP Park95
Expert 1100 points
Part Number: TDA2E

Hi ,

The other part is not different from the reference circuit, but the connection of LDQS, LDQS #, UDQS, UDQS # of the second DDR3 (U23) is designed by changing DQS 2 and 3 in the CPU standard.

Is this the part that affects DRAM operation?

If there is a problem, please check if there is a way to resolve by SW change without changing HW.

Please refer to the red part in the figure below.

  • 0
    TI__Mastermind 38490 points

    For a DDR3 configuration with TDA2x, you can swap bytes provided that all signals within that byte lane (DQSx, DQMx, DQ[x*8+7:x*8], where x is an integer between 0 and 3) are routed to the same byte of the DDR memory. 

    Based on the schematic, it appears that DQS3 and DQM3 are routed to the lower byte of the DDR memory, but the corresponding data bits (DQ31:DQ24] were routed to the upper byte of the DDR memory. This is not a supported configuration, and there is not a software work-around. Thus, a hardware change would be required.

    Best regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 1100 points
    Hi Kevin,
    Thanks for your explain.
    My issue is cleaed thanks to your answer.
    Best regards,
    JP