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RTOS/AM5726: AM57xx UART with DMA communication error during million test

Part Number: AM5726


Hi Champs,

When customer uart communication test for million times, it occur sometimes communication error.

We confirmed Tx data success to send to Rx.

AM572x RX side failed data.  We are still investigating this detail. 

Have you ever seen such a issue that failed receive data ?

<communication image>

AM572x RX -----------Tx device

  • Part Number: AM5726

    Tool/software: TI-RTOS

    Hi Champ,

    We are using UART with DMA mode.

    We have two questions.

    1) Despite of "invalidate cache"  on Rx buffer before receiving DMA data, sometimes the cache is automatically enable before reading data 

    Do you have any experience such a phenomenon ?

    Here is detail phenomenon.

    DMA receive setting is following bellow step,

    1: RX buffer cache invalidate

    2: Start receive data

    3: Complete receive

    4: Read out Rx buffer.

    In this case ,it set Rx buffer value to align to cache line size and set multiple length of cache line size for buffer size.

    Our understanding during 1 and 4 invalidated "cache". Usually, system is working correctly.

    However, 1 times per 1million times communication,  cache is automatically "validated"  during "2~4 " and read previous data. 

    We confirmed 1~4 process didn't access to Rx buffer on the PGM.

     

    Regards,

    Kz777

  • Hi , you summarize two question. Howeve,r each of question is independent. And so sorry, this is not RTOS issue.
    So, it mainly UART DMA issue. and I removed RTOS tag.
  • Hi,

    Please give the details:
    - which Processor SDK RTOS released is used?
    - How do you enable the DMA for UART?
    - Which UART library is linked to the application?
    - Do you use the DMA in callback mode or block mode?
    - What core you run?
    - Do you refer to any TI UART test example, like UART_BasicExample_idkAM572x_DMA_armTestproject?

    We found an issue recently that the UART DMA is not properly tested because the non-DMA support library is specified in the .cfg file and used. The correction will be in the .cfg file like below:

    var Uart = xdc.loadPackage('ti.drv.uart');
    Uart.Settings.enableProfiling = true;
    Uart.Settings.socType = socType;
    Uart.Settings.useDma = "true";

    We also find that on A15, even you do a DMA RX buffer aligned with cache line size with buffer length equals multiple cache line, below operation doesn't always has the data received by A15:

    1. memset/initialize the RX buffer
    2. Cache_wbInv() of the Rx buffer
    3. DMA moved data into RX buffer (we know the data indeed arrived by verifying the memory with CCS memory physical view)
    4. CPU tried to read the data

    There are chance that step 4 didn't get correct data.

    We suggested that add a step right before step 4:
    Cache_Inv() the Rx buffer. That is, invalidate the data buffer before CPU read. Even though there is no operation from CPU (A15) as A15 has speculative fetch and hence it can fetch stale data without CacheInv after DMA fills up this buffer.

    Hope this is the same issue you experienced and thus can be resolved.

    Regards, Eric
  • Hi,

    Any update?

    Regards, Eric
  • Hi Eric,

    Sorry for my late information.

    When I asked above your question, and advice them following action. They accept this action.

    And they will check following action. When they still have problem, I will try to get your required information again.

    We found an issue recently that the UART DMA is not properly tested because the non-DMA support library is specified in the .cfg file and used. The correction will be in the .cfg file like below:

    var Uart = xdc.loadPackage('ti.drv.uart');
    Uart.Settings.enableProfiling = true;
    Uart.Settings.socType = socType;
    Uart.Settings.useDma = "true";

    We also find that on A15, even you do a DMA RX buffer aligned with cache line size with buffer length equals multiple cache line, below operation doesn't always has the data received by A15:

    1. memset/initialize the RX buffer
    2. Cache_wbInv() of the Rx buffer
    3. DMA moved data into RX buffer (we know the data indeed arrived by verifying the memory with CCS memory physical view)
    4. CPU tried to read the data