TMS320C6678: Enabling Prefetch for MSMC memory in OpenMP runtime... Should be disabled ?

Part Number: TMS320C6678

Hello, 

I`ve run my eyes through the C667x OpenMP runtime and noticed that the runtime enables the prefetch feature for MSMC memory which is configured as cache.

C:\ti\openmp_dsp_c667x_2_06_02_01_debug\packages\ti\runtime\ompbios\OpenMP.c

void __TI_omp_reset_rtsc_mode(void)
{
    // Cache configured via ti_sysbios_family_c66_Cache_Module_startup using
    // sizes specified in Platform.xdc
    //__TI_omp_configure_caches();

    /* OMP runtime requires a portion of MSMCSRAM to be non-cached. Since it is 
     * not possible to disable caching in the MSMCSRAM address range, we need a 
     * 2 step process:
     * 1. Map a portion of MSMCSRAM into a range that can be marked as
     *    non-cached. This is done using the MPAX register
     * 2. Annotate the mapped section as non-cached using the appropriate
     *    MAR register for that memory range
     * All accesses to MSMCSRAM through the mapped address range will not
     * be cached.
     */
    if (OpenMP_hasMsmc)
    {
       __TI_setMPAX(OpenMP_mpaxForMsmcMapping, 
                    OpenMP_msmcNoCacheVirtualBase, 
                    OpenMP_msmcNoCachePhysicalBase, 0x10 /* 128 KB */);
       __TI_omp_disable_caching(OpenMP_msmcNoCacheVirtualBase, 
                                OpenMP_msmcNoCacheVirtualSize);

       /* Enable Caching for MSMCSRAM */
       __TI_omp_enable_caching(OpenMP_msmcBase, OpenMP_msmcSize);
    }
    else
    {
       __TI_omp_disable_caching(OpenMP_ddrNoCacheBase, OpenMP_ddrNoCacheSize);
    }

    /* Enable caching for DDR */
    __TI_omp_enable_caching(OpenMP_ddrBase,  OpenMP_ddrSize);
}

And __TI_omp_enable_caching function in C:\ti\openmp_dsp_c667x_2_06_02_01_debug\packages\ti\runtime\openmp\src\omp_init.c looks like:

void __TI_omp_enable_caching(unsigned int start, unsigned int length)
{
tomp_setMAR(start, length, CACHE_PC|CACHE_PFX|CACHE_WTE);
}

I feel Prefetch should be disabled for MSMC memory because of Errata Advisory 28. It says like this for the workaround:

Software must disable the PFX bits in the MARs for address ranges 0x0C000000 – 0x0FFFFFFF corresponding to cacheable data (MARs can be written to only in supervisor mode. The PFX bit for MARs 12-15 which define attributes for 0x0C000000 – 0x0FFFFFFF is set to 1 by default). This will disable pre-fetching for accesses to those addresses, while still allowing those accesses to be cached in L1D. If pre-fetching for MSMC SRAM and other memory spaces is desired, it can still be done provided they are remapped to a space other than 0x0C00 0000 – 0x0FFF FFFF within the MPAX registers (the remapped MSMC will act as shared level 3 memory and will be cacheable in L1D and L2). The L2 cache must remain on and set to a cache size greater than zero, and must not be frozen when accessing pre-fetchable data, otherwise XMC will apply the previously described L1D-specific behavior for the data prefetcher and subject the system to the same issue.

So, I`ve suggested the customer who is actually using OpenMP runtime to rebuild it with the following customization:

1. Add the following function:

void __TI_omp_enable_caching_withoutPFX(unsigned int start, unsigned int length)
{
tomp_setMAR(start, length, CACHE_PC|CACHE_WTE);
}

2. And replace the existing code with it:

void __TI_omp_reset_rtsc_mode(void)
{
    // Cache configured via ti_sysbios_family_c66_Cache_Module_startup using
    // sizes specified in Platform.xdc
    //__TI_omp_configure_caches();

    /* OMP runtime requires a portion of MSMCSRAM to be non-cached. Since it is 
     * not possible to disable caching in the MSMCSRAM address range, we need a 
     * 2 step process:
     * 1. Map a portion of MSMCSRAM into a range that can be marked as
     *    non-cached. This is done using the MPAX register
     * 2. Annotate the mapped section as non-cached using the appropriate
     *    MAR register for that memory range
     * All accesses to MSMCSRAM through the mapped address range will not
     * be cached.
     */
    if (OpenMP_hasMsmc)
    {
       __TI_setMPAX(OpenMP_mpaxForMsmcMapping, 
                    OpenMP_msmcNoCacheVirtualBase, 
                    OpenMP_msmcNoCachePhysicalBase, 0x10 /* 128 KB */);
       __TI_omp_disable_caching(OpenMP_msmcNoCacheVirtualBase, 
                                OpenMP_msmcNoCacheVirtualSize);

       /* Enable Caching for MSMCSRAM */
//       __TI_omp_enable_caching(OpenMP_msmcBase, OpenMP_msmcSize);
       __TI_omp_enable_caching_withoutPFX(OpenMP_msmcBase, OpenMP_msmcSize);
    }
    else
    {
       __TI_omp_disable_caching(OpenMP_ddrNoCacheBase, OpenMP_ddrNoCacheSize);
    }

    /* Enable caching for DDR */
    __TI_omp_enable_caching(OpenMP_ddrBase,  OpenMP_ddrSize);
}

Do you agree with this customization ? If yes, please consider updating the OpenMP runtime in the future release.

Best Regard,
NK