1. What is the Pros and Cons of multiple-way set associative cache?
My understanding after reading the TI's documents is follows:
Pros: Reduce the conflict cache misses because the most-recently-used data has less possibility to be evicted.
Cons: Some overhead due to the conditioning of the multiple ways and setting the LRU bit.
So if the cache misses is too much, we tend to use more-way set associative caches, e.g., L2 has 4-way set associative caches. L1D use 2-way set-associative caches.
Please correct my understanding.
2. What is the cache misses for L2?
3. Why L1D (64 bytes) has smaller cache line than L2's (128 bytes)?
My understanding: Smaller cache line is fast in fetching new data but suffers from more conflict misses. Please correct my understanding.