Tool/software: TI-RTOS
I have looked at the below RTOS SDK
pdk_am57xx_1_0_9
and Doc
spruhz7h.pdf
AM571x(SR2.0,SR1.0) AM570x(SR2.1,SR2.0)
SitaraTM Processors
Technical Reference Manual
Literature Number: SPRUHZ7H
August 2015?Revised May 2018
Chapter 25 eMMC/SD/SDIO
25.4.5 DMA Modes
25.4.5.1 Master DMA Operations
Because I use ADMA, but ADMA is not working.
Interrupt Status Register MMCHS_STAT[0] CC BIT is completed, but MMCHS_STAT[1] TC BIT is No transfer complete.
Do you have any missing considerations in running ADMA?
It is implemented by the method shown in 25.4.5.1 Master DMA Operations and 25.5.1.2.1.3 Read/Write Transfer Flow in DMA Mode With Polling.
It is necessary to set for registers not described as ADMA, DMA in the technical manual?
Consider interrupts? etc..
Is there anything necessary to running it?
Customized source code excerpt:
-------------------------------------------
typedef struct {
uint16_t attribute;
uint16_t length;
uint32_t address;
} sdhUsdhcAdmaBd_t;
//ADMA Descriptor Table
sdhUsdhcAdmaBd_t adma_descriptor_table[100];
.
.
.
static MMCSD_Error MMCSD_v1_transfer(MMCSD_Handle handle,
MMCSD_v1_Transaction *transaction)
.
.
.
MMCSD_osalCache_wbInv(object->dataBufIdx,(transaction->blockSize * transaction->blockCount));
for(i=0;i<(transaction->blockCount/127) + ((transaction->blockCount%127 != 0) ? 1:0);i++){
adma_descriptor_table[i].address =(uint32_t)MMCSD_soc_l2_global_addr((uint32_t)&object->dataBufIdx[i*0xFE00]);
adma_descriptor_table[i].length = (uint16_t)(0xFE00);
adma_descriptor_table[i].attribute = (uint8_t) (0x20 | 0x01);
}
adma_descriptor_table[i-1].attribute |= 0x02;
if(transaction->blockCount%127 != 0){
adma_descriptor_table[i-1].length = (uint16_t)(transaction->blockCount%127)*512;
}
MMCSD_osalCache_wbInv(adma_descriptor_table,sizeof(adma_descriptor_table));
/* Set MMCHS ADMASAL register.*/
MMCSDAdmaSetADMASAL(hwAttrs->baseAddr,(uint32_t)MMCSD_soc_l2_global_addr((uint32_t)adma_descriptor_table));
/* Others Register setting used for ADMA */
MMCSDAdmaSetRegister(hwAttrs->baseAddr);
.
.
.
HSMMCSDCommandSend(hwAttrs->baseAddr, &cmdObj);
.
.
.
void MMCSDAdmaSetADMASAL(uint32_t mmcsdBase, const uint32_t address)
{
HW_WR_REG32((mmcsdBase + CSL_MMCHS_ADMASAL), address);
}
void MMCSDAdmaSetRegister(uint32_t mmcsdBase )
{
uint32_t regVal = 0U;
HSMMCSDIntrStatusEnable(mmcsdBase, HS_MMCSD_INTR_MASK_ADMAERROR);
HSMMCSDIntrStatusEnable(mmcsdBase, HS_MMCSD_INTR_MASK_DMA);
regVal = HW_RD_REG32(mmcsdBase + CSL_MMCHS_CON);
regVal |= CSL_MMCHS_CON_DMA_MNS_MASK;
HW_WR_REG32((mmcsdBase + CSL_MMCHS_CON), regVal);
regVal = HW_RD_REG32(mmcsdBase + CSL_MMCHS_HCTL);
regVal |= 0x10;
HW_WR_REG32((mmcsdBase + CSL_MMCHS_HCTL), regVal);
}
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