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EMIFA access (Read/write) effect on DMA operation [C674x DSP]

LUCENT-Has
Prodigy 50 points

Other Parts Discussed in Thread: TMS320C6747

Dear experts,

I am using TMS320C6747 on a project, there is an EDMA engine for accessing data via McASP and it works without any problem, as soon as I try to access EMIFA through CPU (this is a 32 bit read/write every few milliseconds so there is no need for DMA, etc), this causes corruption on data received from MsASP and I have difficulty to figure out what is really happening and why so little access to EMIFA messes up the DMA operation, I appreciate any comment/sugestions on this issue.

 

Regards,

Lhas

  • 0
    TI__Guru*** 125430 points

    The "System Interconnect" chapter in the System Reference Guide shows the overall hookup of all the peripherals.  In particular take a look at bridge 3 (BR3) and bridge 4 (BR4).  If you look at the path for the CPU to access EMIFA and the path for EDMA to access McASP, you'll notice that BR3 and BR4 are in both paths.  In other words, there's a conflict here.  That said, you need to optimize your accesses.

    A couple recommendations:

    • Look at your EMIFA timings (e.g. setup, hold, strobe).  Make sure you're not using the default timings (very slow and long) and that will tie up the bus (and correspondingly BR3/BR4) for long periods of time.  Optimizing your EMIFA timing will also reduce the amount of time the EDMA is held off from servicing the McASP.
    • Be sure to utilize the FIFO for the McASP.  This will make you less sensitive to any latency introduced by CPU reads to EMIFA

     

  • 0 in reply to Brad Griffis
    Prodigy 50 points

    Thanks Brad,

    The EMIF timing is comnfigured correctly for the device which is currently connected to this interface (it's not the default CFG).

    I don't miss any data from EDMA receving the McASP data but they get corrupted as soon as EMIFA is accessed. I am still baffled to belive that 4 16bit data access / 10 milliseconds can mess up the EDMA operation although both data access use the same shared bridges.

    Thanks and looking forward to any tips/hints,

    Lhas

     

     

  • 0 in reply to LUCENT-Has
    TI__Guru*** 125430 points

    Sorry for the delayed response.  I've been traveling and had hoped someone else might jump in!  (Come on, guys!)

    So can you please show an example data stream that you receive, e.g. what you expect to receive vs what you actually receive?  It might be important to see exactly how it's being corrupted, i.e. is it a bit flip, a repeated sample, etc?

  • 0 in reply to Brad Griffis
    Prodigy 50 points

    Hello Brad,

    Thanks for getting back to me, the data has three different patterns when corrupted from repeated random signal to sometimes being completely zero and periodic signals at some ocassion but this three patterns are what is observed at all times.

    I haven't spent more time on this issue as I had other things to do but it would be helpful if someone who has had similar experiences, share the results.

    Best regards,

    Lhas

     

     

     

     

     

  • 0 in reply to LUCENT-Has
    Prodigy 60 points

    Hello  LUCENT-Has ,

    I met the same problem either.I use EMIFA access FRAM,and EDMA is used to transfer SPI data.And when I access FRAM,DMA missed one SPI data because SPI data is overlapped.I don't know how it happens?(SPI transfers one data needs 2us,but EMIFA access FRAM only need 400ns.)

    Best regards,

    RJY

  • 0 in reply to Jun3
    TI__Mastermind 35645 points

    Hi,

    Please create a new thread for this issue since this is a closed thread. In order to reopen the issue, i would suggest to create a new post, so that, you would get chance to pay more attention to new thread instead of older one.

    Thanks & regards,
    Sivaraj K

  • 0 in reply to Sivaraj Kuppuraj
    Genius 3555 points

    Hi Sivaraj,

    Could you please provide the sample code how to control EMIFA over EDMA?

    Thanks in advance.

    B.R.

    OC