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66AK2G12: DDR3L configuration in Default Gel file... Are CL=7 and CWL=5 invalid configuration ?

Naoki Kawada
Guru 19890 points
Part Number: 66AK2G12

Hi,

The default configurations for CL and CWL are in ddr3A_setup_1066 function in gel file (C:\ti\ccsv8\ccs_base\emulation\boards\evmk2g\gel\evmk2g_arm.gel):

	// Program BL=0, CL, WR, and PD=1 in the Mode Register 0 (address offset 0x054).
	// All other fields must be left at their default values.
	DDR3A_MR0 = 0x00001830;		//0x00001430; //MM - calculated: 0x00001430, orig: 0x00001420 //-CL - 6, CWL - 5

	// Program DIC, RTT, and TDQS in the Mode Register 1 (address offset 0x058).
	// All other fields must be left at their default values.

	DDR3A_MR1 = 0x00000006;

	// Program Mode Register 2 (address offset 0x05C).
	// Maintaining default values of Program Mode Register 2
	//DDR3A_MR2 = 0x00000018;

As you see, DDR3A_MR0 is configured as 0x00001830 and DDR3A_MR2 is no update (keeping default value). This means, CL=7 and CWL=5 are configured for 1066Mhz speed bin, but JEDEC suggests this combination should be reserved: 

How should we handle this issue ?

Best Regards,
NK

  • 0
    TI__Genius 9065 points
    Hello Naoki,

    Due to the US holidays, on this particular E2E thread, our response may get delayed until the week of Jan 2, 2019.

    Warmest Wishes for Happy Holidays and a Happy New Year!

    best regards,
    David Zhou
  • 0
    TI__Guru** 115880 points
    Kawada-san,

    I have forwarded this question to the DDR/EMIF expert. As far as I know the intent in the GEL was to set CL = 6 and CWL =5 but as you indicated the setting seems to be marking CL=7 and CWL =5 which doesn`t seem correct based on the spec you have provided. I think this needs to be fixed in the GEL but I will let the DDR expert confirm before I raise a bug for this issue.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    TI__Guru** 115880 points

    Kawada-san,

    I consulted with my colleague on this DDR setting and after cross-checking the JEDEC spec and the Micron datasheet , we agree that for DDR3L-1066, the CL can be either 7 or 8 and the CWL needs to be 6. Based on this, the recommendation is that the GEL be modified to set it for CL=7 and CWL=6 for optimal performance at DDR3L-1066.

    You can update the GEL to following to fix the issue:

    // Program Mode Register 2 (address offset 0x05C).
    // Maintaining default values of Program Mode Register 2
    DDR3A_MR2 = 0x00000008;


    Thanks for bringing this issue to our attention.

    Regards,
    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 19890 points
    Hi Rahul-san,

    Thanks for your confirmation. This answers to my question. I close the thread now.

    Best Regards,
    NK