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Linux/AM3359: Ethernet PHY 1Gbps not working

Part Number: AM3359

Tool/software: Linux

Hi,

In TI AM3359 Processor, facing issue in External Ethernet PHY(Marvell 88E1510) with 1Gbps Speed. When PHY is connected to 1Gbps hub/PC the link is up and down frequently. when forcing it to 100Mbps and 10Mbps it is working fine.

The device tree details are as follows,

                mac: ethernet@4a100000 {
                        compatible = "ti,am335x-cpsw","ti,cpsw";
                        ti,hwmods = "cpgmac0";
                        clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
                        clock-names = "fck", "cpts";
                        cpdma_channels = <8>;
                        ale_entries = <1024>;
                        bd_ram_size = <0x2000>;
                        no_bd_ram = <0>;
                        mac_control = <0x20>;
                        slaves = <2>;
                        active_slave = <1>;
                        cpts_clock_mult = <0x80000000>;
                        cpts_clock_shift = <29>;
                        reg = <0x4a100000 0x800
                               0x4a101200 0x100>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        interrupt-parent = <&intc>;
                        /*
                         * c0_rx_thresh_pend
                         * c0_rx_pend
                         * c0_tx_pend
                         * c0_misc_pend                

                         */
                        interrupts = <40 41 42 43>;
                        ranges;
                        syscon = <&scm_conf>;
                        status = "disabled";

                        davinci_mdio: mdio@4a101000 {
                                compatible = "ti,cpsw-mdio";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                ti,hwmods = "davinci_mdio";
                                bus_freq = <1000000>;
                                reg = <0x4a101000 0x100>;
                                status = "disabled";

                                ethernet-phy@0 {
                                        compatible = "marvell,88E1112","ethernet-phy-ieee802.3-c22";
                                        device_type = "ethernet-phy";
                                        reg = <0>;
                                };
                                ethernet-phy@1 {
                                        compatible = "marvell,88E1112", "ethernet-phy-id0141.0dd0", "ethernet-phy-ieee802.3-c22";
                                        device_type = "ethernet-phy";
                                        reg = <1>;
                                };
                        };

                        cpsw_emac0: slave@4a100200 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };

                        cpsw_emac1: slave@4a100300 {
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };

                        phy_sel: cpsw-phy-sel@44e10650 {
                                compatible = "ti,am3352-cpsw-phy-sel";
                                reg= <0x44e10650 0x4>;
                                reg-names = "gmii-sel";
                        };
&cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
        phy-mode = "rmii";
        dual_emac_res_vlan = <1>;
};

&davinci_mdio {
        pinctrl-names = "default";
        pinctrl-0 = <&mdio_pins>;
        status = "okay";
};

&mac {
        slaves = <1>;
        pinctrl-names = "default";
        pinctrl-0 = <&ethernet0_pins>;
        status = "okay";
};

Thanks & Regards,

Arunkumar M

  • Hi Arunkumar,

    Do you use AM335x TI PSDK Linux? If yes, which version?

    Do you observe this issue (1Gbps not working) in both u-boot and Linux, or in Linux only? I would suggest you to check how 1Gbps works in u-boot stage first.

    Also I see you are using RMII mode, and this mode support only 10/100 Mbps speed, check AM335x TRM, section 14.3.5 RMII Interface

    Regards,
    Pavel
  • Hi Pavel,

    Thanks for the reply,

    I am using Linux version of 4.4.19. Eth0 is connected to RMII and Eth1 is connected RGMII2 (88E1510 PHY) and RGMII2 is configured in device tree is mentioned below

    &cpsw_emac1 {
    phy_id = <&davinci_mdio>, <1>;
    phy-mode = "rgmii-id";
    dual_emac_res_vlan = <1>;
    };

    since AM3359 MAC do not support RGMII delay addition, We are using the delay feature in PHY and we apply delay in both rx and tx lanes.
    Our boot loader is a barebox instead of Uboot, there also link works fine up to 100Mbps only.

    when we tried to probe the RX CLK & TX CLK, the RX CLK from PHY generates a constant 125MHz clock whereas the TX CLK from AM3359 MAC generates 25MHz clock while 1G link is down and 125MHz while 1G link is up. The 1G link remains up for approximately 1-2 seconds and then drops down to 25MHz. We suspect does the MAC trying to force the link to be 100Mbps?.

    In the clock out domains as mentioned in technical reference manual, the RMII works with CPSW-50MHz clock whereas the RGMII 1G works
    with CPSW-250MHz RGMII CLOCK. whether I can use eth0 RMII in 10/100 Mbps and eth1 in RGMII 10/100/1000 Mbps mode parllely ?

    Regards,
    Arunkumar M
  • Hi Arunkumar,

    Yes, you can use eth0 in RMII 10/100 Mbps mode and eth1 in RGMII 10/100/1000 Mbps mode in parallel. Just make sure you have the correct value in below Control Module register:

    GMII_SEL[1:0] gmii1_sel = 0x1
    GMII_SEL[3:2] gmii2_sel = 0x2

    Make sure also you are providing 250Mhz clock from Core PLL to CPSW module (MHZ_250_CLK).

    Regards,
    Pavel
  • Hi Pavel,

    Thanks for the reply,

    How to ensure 250MHz clock is provided between core PLL to cpsw.

    CORE_CLKOUTM5/2 is feeded ror cpsw_125mhz_gclk in device tree mac which is located in am33xx-clocks.dtsi

    Regards,

    Arunkumar M

  • Arun,

    You can check Core PLL settings with omapconf tool. Check below doc for more info regarding this tool usage:

    www.ti.com/.../sprac74a.pdf
    3.3.3.2 OMAPCONF

    Also you can align your DTS file to Phytec AM335x PCM-953 board, which has similar configuration: EMAC0 in RMII mode and EMAC1 in RGMII-ID mode.

    linux-kernel/arch/arm/boot/dts/am335x-pcm-953.dtsi
    linux-kernel/arch/arm/boot/dts/am335x-phycore-rdk.dts
    linux-kernel/arch/arm/boot/dts/am335x-phycore-som.dtsi

    Regards,
    Pavel
  • Hi Pavel,

    Thanks for the reply, 

    We are verified with OMAP config tool which is attached along here,  for "omapconf show dpll" command it is showing M5 clock is Enabled with 250MHz but in "omapconf export ctt is showing M5 Clock Gated, see the attachment for utility dumb of 0x44E00484 is 0x00000228

    But still we are facing the problem in 1Gbps up.

    DTS file whatever you mentioned same only we are using.

    Regards,

    Arunkumar M

    root@phycore-r2-am335x-5:/home# ./omapconf show dpll
    OMAPCONF (rev 1.73-nogit built Tue Jan 8 16:52:47 IST 2019)
    
    HW Platform:
      Generic AM33XX (Flattened Device Tree)
      AM3359 ES2.1 GP Device (UNKNOWN performance ZCZ package (800MHz))
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
    Error: I2C Read failed
      UNKNOWN POWER IC
    Error: I2C Read failed
      UNKNOWN AUDIO IC
    
    SW Build Details:
      Build:
        Version:  ____   _   _ __   __ _____  _____   ____
      Kernel:
        Version: 4.4.19-AM335x-PD16.2.0
        Author: root@ITT097
        Toolchain: gcc version 4.7.3 20121106 (prerelease) (OSELAS.Toolchain-2012.12.1 linaro-4.7-2012.11)
        Type: #18
        Date: Fri Jan 4 19:53:33 IST 2019
    
    |--------------------------------------------|
    | DPLL Configuration         | DPLL_PER      |
    |--------------------------------------------|
    | Status                     | Locked        |
    |                            |               |
    | Mode                       | Lock          |
    | Automatic Control          | Not Supported |
    |  LPST = Low-Power STop     |               |
    |  LPBP = Low-Power ByPass   |               |
    |  FRBP = Fast-Relock ByPass |               |
    |  MNBP = MN ByPass          |               |
    |                            |               |
    | Sigma-Delta Divider        | 4             |
    | SELFREQDCO                 | 0             |
    |                            |               |
    | Ref. Frequency (MHz)       | 25.000        |
    | M Multiplier Factor        | 960           |
    | N Divider Factor           | 24            |
    | Lock Frequency (MHz)       | 960           |
    |                            |               |
    | CLKOUT Output              |               |
    |   Status                   | Enabled       |
    |   Clock Divider            | 5             |
    |   Clock Speed (MHz)        | 192           |
    |                            |               |
    | CLK_DCO_LDO Output         |               |
    |   Status                   | Enabled       |
    |   Clock Speed (MHz)        | 960           |
    |                            |               |
    |--------------------------------------------|
    
    |---------------------------------------------------------------------------------------------|
    | DPLL Configuration          | DPLL_CORE     | DPLL_MPU      | DPLL_DDR      | DPLL_DISP     |
    |---------------------------------------------------------------------------------------------|
    | Status                      | Locked        | Locked        | Locked        | Bypassed      |
    |                             |               |               |               |               |
    | Mode                        | Lock          | Lock          | Lock          | MNBP          |
    | Automatic Control           | Not Supported | Not Supported | Not Supported | Not Supported |
    |  LPBP = Low-Power ByPass    |               |               |               |               |
    |  FRBP = Fast-Relock ByPass  |               |               |               |               |
    |  MNBP = MN ByPass           |               |               |               |               |
    | Low-Power Mode              | Disabled      | Disabled      | Disabled      | Disabled      |
    |                             |               |               |               |               |
    | Automatic Recalibration     | Disabled      | Disabled      | Disabled      | Disabled      |
    | Clock Ramping during Relock | Disabled      | Disabled      | Disabled      | Disabled      |
    | Ramping Rate (x REFCLK(s))  | 2             | 2             | 2             | 2             |
    | Ramping Levels              | No Ramp       | No Ramp       | No Ramp       | No Ramp       |
    |                             |               |               |               |               |
    | Bypass Clock                | CLKINP        | CLKINP        | CLKINP        | CLKINP        |
    | Bypass Clock Divider        |               |               |               |               |
    | REGM4XEN Mode               | Disabled      | Disabled      | Disabled      | Disabled      |
    |                             |               |               |               |               |
    | Ref. Frequency (MHz)        | 25.000        | 25.000        | 25.000        | 25.000        |
    | M Multiplier Factor         | 1000          | 12            | 400           | 0             |
    | N Divider Factor            | 24            | 0             | 24            | 0             |
    | Lock Frequency (MHz)        | 1000          | 300           | 400           | 0 (0)         |
    |                             |               |               |               |               |
    | M2 Output                   |               |               |               |               |
    |   Status                    |               | Enabled       | Enabled       | Gated         |
    |   Clock Divider             |               | 1             | 1             | 1             |
    |   Clock Speed (MHz)         |               | 300           | 400           | 25 (25)       |
    |                             |               |               |               |               |
    | CLK_DCO_LDO Output          |               |               |               |               |
    |   Status                    | Gated         |               |               |               |
    |   Clock Speed (MHz)         | 2000          |               |               |               |
    |                             |               |               |               |               |
    |                             |               |               |               |               |
    | M4 Output                   |               |               |               |               |
    |   Status                    | Enabled       |               |               |               |
    |   Clock Divider             | 10            |               |               |               |
    |   Clock Speed (MHz)         | 200           |               |               |               |
    |                             |               |               |               |               |
    | M5 Output                   |               |               |               |               |
    |   Status                    | Enabled       |               |               |               |
    |   Clock Divider             | 8             |               |               |               |
    |   Clock Speed (MHz)         | 250           |               |               |               |
    |                             |               |               |               |               |
    | M6 Output                   |               |               |               |               |
    |   Status                    | Gated         |               |               |               |
    |   Clock Divider             | 4             |               |               |               |
    |   Clock Speed (MHz)         | 500           |               |               |               |
    |---------------------------------------------------------------------------------------------|
    
    
    
    |--------------------------- ctt dump begin ----------------------|
    DeviceName AM335x1.0
    0x44E00000 0x00004502
    0x44E00004 0x0000000A
    0x44E00008 0x00000101
    0x44E0000C 0x00000056
    0x44E00010 0x00070000
    0x44E00014 0x00000002
    0x44E00018 0x00070000
    0x44E0001C 0x00000002
    0x44E00020 0x00070000
    0x44E00024 0x00000002
    0x44E00028 0x00000002
    0x44E0002C 0x00000002
    0x44E00030 0x00000002
    0x44E00034 0x00030000
    0x44E00038 0x00030000
    0x44E0003C 0x00030000
    0x44E00040 0x00000002
    0x44E00044 0x00030000
    0x44E00048 0x00030000
    0x44E0004C 0x00030000
    0x44E00050 0x00030000
    0x44E00054 0x00030000
    0x44E00058 0x00030000
    0x44E00060 0x00000002
    0x44E00064 0x00020002
    0x44E00068 0x00030000
    0x44E0006C 0x00000002
    0x44E00070 0x00000002
    0x44E00074 0x00030000
    0x44E00078 0x00030000
    0x44E0007C 0x00030000
    0x44E00080 0x00000002
    0x44E00084 0x00030000
    0x44E00088 0x00030000
    0x44E0008C 0x00030000
    0x44E00090 0x00000002
    0x44E00094 0x00030000
    0x44E00098 0x00030000
    0x44E0009C 0x00030000
    0x44E000A0 0x00030000
    0x44E000A4 0x00030000
    0x44E000A8 0x00030000
    0x44E000AC 0x00030000
    0x44E000B0 0x00030000
    0x44E000B4 0x00030000
    0x44E000B8 0x00030000
    0x44E000BC 0x00000002
    0x44E000C0 0x00030000
    0x44E000C4 0x00030000
    0x44E000C8 0x00030000
    0x44E000CC 0x00030000
    0x44E000D0 0x00020002
    0x44E000D4 0x00030000
    0x44E000D8 0x00030000
    0x44E000DC 0x00000002
    0x44E000E0 0x00000002
    0x44E000E4 0x00070000
    0x44E000E8 0x00070000
    0x44E000EC 0x00030000
    0x44E000F0 0x00030000
    0x44E000F4 0x00030000
    0x44E000F8 0x00030000
    0x44E000FC 0x00000002
    0x44E00100 0x00000002
    0x44E00104 0x00030000
    0x44E0010C 0x00030000
    0x44E00110 0x00000002
    0x44E0011C 0x0000007A
    0x44E00120 0x00000002
    0x44E00124 0x00070000
    0x44E00128 0x00030000
    0x44E0012C 0x00000001
    0x44E00130 0x00060002
    0x44E00134 0x00030000
    0x44E00138 0x00030000
    0x44E0013C 0x00030000
    0x44E00140 0x00000001
    0x44E00144 0x00000012
    0x44E00148 0x00000001
    0x44E0014C 0x00000002
    0x44E00150 0x00000012
    0x44E00400 0x00003E06
    0x44E00404 0x00000002
    0x44E00408 0x00030000
    0x44E0040C 0x00000002
    0x44E00410 0x00000002
    0x44E00414 0x12510000
    0x44E00418 0x00000009
    0x44E0041C 0x00000000
    0x44E00420 0x00000001
    0x44E00424 0x00000000
    0x44E00428 0x00000000
    0x44E0042C 0x00000C00
    0x44E00430 0x00000000
    0x44E00434 0x00000001
    0x44E00438 0x00000000
    0x44E0043C 0x00000000
    0x44E00440 0x00019018
    0x44E00444 0x00000000
    0x44E00448 0x00000100
    0x44E0044C 0x00000000
    0x44E00450 0x00000000
    0x44E00454 0x00000000
    0x44E00458 0x00000000
    0x44E0045C 0x00000001
    0x44E00460 0x00000000
    0x44E00464 0x00000000
    0x44E00468 0x0003E818
    0x44E0046C 0x00000000
    0x44E00470 0x00000001
    0x44E00474 0x00000000
    0x44E00478 0x00000000
    0x44E0047C 0x00000300
    0x44E00480 0x0000022A
    0x44E00484 0x00000228
    0x44E00488 0x00000007
    0x44E0048C 0x00000007
    0x44E00490 0x00000007
    0x44E00494 0x00000007
    0x44E00498 0x00000004
    0x44E0049C 0x0403C018
    0x44E004A0 0x00000201
    0x44E004A4 0x00000001
    0x44E004A8 0x00000201
    0x44E004AC 0x00000285
    0x44E004B0 0x00040002
    0x44E004B4 0x00000002
    0x44E004B8 0x00000002
    0x44E004BC 0x00030000
    0x44E004C0 0x00030000
    0x44E004C4 0x00000002
    0x44E004C8 0x00030000
    0x44E004CC 0x00000006
    0x44E004D0 0x00000002
    0x44E004D4 0x00030000
    0x44E00504 0x00000001
    0x44E00508 0x00000001
    0x44E0050C 0x00000001
    0x44E00510 0x00000001
    0x44E00514 0x00000004
    0x44E00518 0x00000001
    0x44E0051C 0x00000001
    0x44E00520 0x00000000
    0x44E00528 0x00000000
    0x44E0052C 0x00000000
    0x44E00530 0x00000000
    0x44E00534 0x00000000
    0x44E00538 0x00000001
    0x44E0053C 0x00000000
    0x44E00600 0x00000006
    0x44E00604 0x00000002
    0x44E00700 0x00000080
    0x44E00800 0x00000002
    0x44E00804 0x00000302
    0x44E00900 0x00000302
    0x44E00904 0x00040002
    0x44E00908 0x00070000
    0x44E0090C 0x00000001
    0x44E00910 0x00030000
    0x44E00914 0x00030000
    0x44E00A00 0x00000001
    0x44E00A20 0x00030000
    0x44E00B00 0x00000000
    0x44E00B04 0x00000500
    0x44E00B08 0x00000000
    0x44E00B0C 0x00000100
    0x44E00B10 0x00000000
    0x44E00C00 0x00000003
    0x44E00C04 0x00000000
    0x44E00C08 0x01E60007
    0x44E00C0C 0xEE0000EB
    0x44E00D00 0x00000000
    0x44E00D04 0x00000008
    0x44E00D08 0x00000000
    0x44E00D0C 0x00000020
    0x44E00E00 0x01FF0007
    0x44E00E04 0x000003F7
    0x44E00E08 0x00000000
    0x44E00F00 0x00000000
    0x44E00F04 0x00001006
    0x44E00F08 0x00000000
    0x44E00F0C 0x78000017
    0x44E00F10 0x00000003
    0x44E00F14 0x00000000
    0x44E00F18 0x00000003
    0x44E00F1C 0x00000000
    0x44E01000 0x00000004
    0x44E01004 0x00000000
    0x44E01100 0x00060047
    0x44E01104 0x00000000
    0x44E01110 0x00000037
    0x44E01114 0x00000001
    0x44E01200 0x00000000
    0x44E01204 0x00000000
    0x44E10040 0x00800373
    |---------------------------- ctt dump end -----------------------|
    
    
    

  • Arunkumar,

    Arun kumar91 said:
    but in "omapconf export ctt is showing M5 Clock Gated, see the attachment for utility dumb of 0x44E00484 is 0x00000228

    Which bit(s) shows that M5 clock is gated? From what I can see, it is enabled:

    CM_DIV_M5_DPLL_CORE/0x44E00484 [9] ST_HSDIVIDER_CLKOUT2 = 0x1 - The clock output is enabled

    CM_PER_L4HS_CLKSTCTRL/0x44E0011C [4] CLKACTIVITY_CPSW_250MHZ_GCLK = 0x1 - Active

    Arun kumar91 said:
    DTS file whatever you mentioned same only we are using.

    But I see your DTS file is very different from the ones I pointed in my previous reply.  Please attach your latest version of DTS file.

    Regards,
    Pavel

  • Hi Pavel,

    I used same DTS only except i updated the portion of ethernet phy which i added in my first post

    Regards,
    Arunkumar M
  • Hi Pavel,

    We found electric error on phy section and corrected and it is working fine.

    Thanks for your valuable support.

    Regards,
    Arunkumar M