Hello.
I would like to use uPP as clock master to connect ADC.
Does anyone let me know, please?
- What is duty cycle of uPP ?
(I expect it is between 45% and 55%)
- Can I use upp as clock master?
Best regards,
RY
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Hello.
I would like to use uPP as clock master to connect ADC.
Does anyone let me know, please?
- What is duty cycle of uPP ?
(I expect it is between 45% and 55%)
- Can I use upp as clock master?
Best regards,
RY
Hi RY,
Yes, duty cycle of uPP is between 45% to 55%. For your information, you can refer to the given link.
Page 234
http://focus.ti.com/lit/ds/symlink/tms320c6748.pdf
Also, uPP can be used as master clock as it works in receive, transmit and duplex mode. For that, you can refer to the following section.
Section 6.26, Page 232
http://focus.ti.com/lit/ds/symlink/tms320c6748.pdf
Best Regards,
Ankit Agrawal
Hello Ankit.
Thank you so much for your advice.
I can not find the duty cycle in datasheet Page 234.
How can I consider about duty cycle?
When 1.3V core voltage, the Table 6-117 of datasheet describes below.
#13 tw(OUTCLKH) : Pulse width, CHn_CLK high .. SDR mode 5ns[MIN], DDR mode 10ns[MIN]
#14 tw(OUTCLKL) : Pulse width, CHn_CLK low .. SDR mode 5ns[MIN], DDR mode 10ns[MIN]
Does it mean 50% of duty cycle?
From your answer, it is 45%-55%.
Which does it mean 5% of error need to be considered ?
Best regards,
RY