RTOS/TDA2: DSP: DDR and L2SRAM communication using edma

Kajal Karande

Part Number: TDA2

Tool/software: TI-RTOS

Hello,

I am using Processor SDK 3.0 .

I want to transfer data to L2SRAM from DDR and vice versa using edma on DSP. For configuring EDMA, I'm referring framecopy link ( frameCopyAlgoLocalDma.c file)

While transferring data from DDR, dst address will be L2SRAM ( that is 0x40800000 ), so I have configured edma as,

-------

#define DSP1_L2SRAM_ADDR 0x40800000
.

//configuration for write data to l2sram

       pAlgHandle->pParamSet->destAddr   = DSP1_L2SRAM_ADDR;
        pAlgHandle->pParamSet->srcAddr    = (UInt32)inPtr[0];
        pAlgHandle->pParamSet->srcBIdx    = inPitch[0];
        pAlgHandle->pParamSet->destBIdx   = inPitch[0];
        pAlgHandle->pParamSet->srcCIdx    = 0;
        pAlgHandle->pParamSet->destCIdx   = 0;
        pAlgHandle->pParamSet->aCnt       = lineSizeInBytes;
        pAlgHandle->pParamSet->bCnt       = height/NUM_OF_SLICE;
        pAlgHandle->pParamSet->cCnt       = 1; //no. of frames
        pAlgHandle->pParamSet->bCntReload = height/NUM_OF_SLICE;
        pAlgHandle->pParamSet->opt        = opt;
        pAlgHandle->pParamSet->linkAddr   = 0xFFFF;

//configuration for write data back to ddr
         pAlgHandle->pParamSet->destAddr   = (UInt32)outPtr[0];
         pAlgHandle->pParamSet->srcAddr    = DSP1_L2SRAM_ADDR;
         pAlgHandle->pParamSet->srcBIdx    = outPitch[0];
         pAlgHandle->pParamSet->destBIdx   = outPitch[0];
         pAlgHandle->pParamSet->srcCIdx    = 0;
         pAlgHandle->pParamSet->destCIdx   = 0;
         pAlgHandle->pParamSet->aCnt       = lineSizeInBytes;
         pAlgHandle->pParamSet->bCnt       = height/NUM_OF_SLICE;
         pAlgHandle->pParamSet->cCnt       = 1;
         pAlgHandle->pParamSet->bCntReload = height/NUM_OF_SLICE;
         pAlgHandle->pParamSet->opt        = opt;
         pAlgHandle->pParamSet->linkAddr   = 0xFFFF;

---------

Issue is,

There is no transfer happening between DDR and L2SRAM ( no data display on output screen). I don't get any compile time errors also at rum time. I checked statistics, SCI_DSP1_EDMA not consuming not even L2SRAM is used.

What else I need to do to get this working?

What is this >> SCI_DSP1_EDMA ?

Regards,

Kajal

over 6 years ago

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi Kajal,

SCI_DSP1_EDMA refers to DSP's EDMA. Each DSP has it's own EDMA which can also be used instead of EDMA.
Please see TRM for more details on DSP's EDMA.
The L2 memory can be split into L2 RAM (normal addressable on-chip memory) and L2-cache.
Can you check what is L2CFG to see if you have indeed set L2MODE to 0?

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hello Rishabh,

Where I will get this TRM for DSP's EDMA ?

Can you check what is L2CFG to see if you have indeed set L2MODE to 0?

>> In which file L2CFG or L2MODE is defined?

I got "L2MODE" term in >> vision_sdk/build/rtos/tda2xx/config_c66.bld:78: l2Mode: "32k", did you mean this file ?

Regards,

Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

You can see TDA2 TRM.
L2CFG is a DSP register.
Please see CorePac DSP spec (link is given in TDA2 TRM DSP chapter).

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hello Rishabh,

Can you please point me at specific TRM for DSP's EDMA ?

What about ,

>> In which file L2CFG or L2MODE is defined?

I got "L2MODE" term in >> vision_sdk/build/rtos/tda2xx/config_c66.bld:78: l2Mode: "32k", did you mean this file ?

Where to check L2MODE is set to 0 or not ??

Regards,

Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

TDA2 TRM is here: www.ti.com/.../sprui29f.pdf
You should read chapter 5 to find MMRs.

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hello Rishabh,

setting l2Mode: "0" , doesn't get any data transmission.
Note :- I have changed in vision_sdk/build/rtos/tda2xx/config_c66.bld file for DSP1 .
Can you please suggest more, what need to do?

Regards,
Kajal

0 Kajal Karande over 6 years ago in reply to Kajal Karande

Expert 1655 points

At vision sdk level, can I see value of L2CFG register ? ( with out debugging though CCS)
Regards,
Kajal

0 Kajal Karande over 6 years ago in reply to Kajal Karande

Expert 1655 points

Any Update??
Regards,
Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

What is the API you are using to do the transfer?
System EDMA and local EDMA both are integrated in Vision SDK.
Please see PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\links_fw\src\rtos\utils_common\src\utils_dma.c and PROCESSOR_SDK_VISION_03_05_00_00\vision_sdk\links_fw\src\rtos\utils_common\src\dma_cfg\utils_dma_cfg_dsp1.c.

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hi Rishabh,

I want to local EDMA API for DSP.
I'm referring frameCopy link for transferring.
What's difference between that APIs and suggested by you?
Which one shall I use?

Regards,
Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

I would suggest you to use Utils API.

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hi Rishabh,

Utils APIs are the wrappers , internally it calls EDMA3LLD APIs. (correct me if I'm wrong)

Do you have any concern to suggest utils API?

In my case, I'm calling directly EDMA APIs, but still data transfer is not happening.

----------------

One more thing I noticed while debugging is,

1. When I use dst address as DSP2's L2SRAM i.e. 0x41000000, data transfer happens ( Execution is on DSP1 only).

2. and vice versa.

How is this possible ?

Regards,

Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

It seems that each DSP can access it's L2SRAM using the local address and not via the L3. Hence you can access DSP2's SRAM from DSP1 using L3 and vice versa. A simple experiment to confirm this would be trying to access DSP1's RAM from DSP1 using memory browser. You should be able to access via internal view and not L3.

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hi Rishabh,

DSP1' SRAM :- 0x40800000

DSP2's SRAM :- 0x41000000

Are above local addresses correct? ( these addresses i referred from map file >> mem_segment_definition_bios.xs)

If not can you point me place where I will get map for local addresses.

Regards,

Kajal.

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

0x40800000 and 0x41000000 are L3 addresses. For DSP the local address is 0x0080_0000.
You can see chapter DSP Memory Map in TDA2 TRM.

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

Hi Kajal,

There is another way to do the EDMA. You can use DSPx EDMA (each DSP has it's own) and give the local address (0x0080_0000).

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hello Rishabh,

Regarding your second last post,

0x40800000 and 0x41000000 are L3 addresses. For DSP the local address is 0x0080_0000.
You can see chapter DSP Memory Map in TDA2 TRM.

>> what if both DSPs want to access the same l2 sram address at the same time?

Regards,

Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Kajal,

Using local address you will be able to access only local DSP's L2 SRAM.
To access the other DSP's ram you need to use L3 address.

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Yes, but both DSPs are having their local memory, so there will be two different local addresses, right? ( please correct if I'm wrong)

In TRM, for each one's local memory, i haven't found their addresses.

Regards,

Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

Local address is same for both DSPs. If you access 0x0080_0000 from DSP1 you will be accessing DSP1's memory and vice versa for DSP2.
Local accesses don't go to interconnect hence there is no issue with same address.

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

Hi Kajal,

As this issue is resolved kindly mark the relevant posts as "This resolved my issue" and close the thread.

Regards,
Rishabh

0 Kajal Karande over 6 years ago in reply to Rishabh Garg

Expert 1655 points

Hello Rishabh ,

I have one more doubt,

Can you check what is L2CFG to see if you have indeed set L2MODE to 0?

where can I get these registers values for L1 and L2 configuration?

Only the CCS, register view is way to see?

If want to set bits for them, how will I do this?

Regards,

Kajal

0 Rishabh Garg over 6 years ago in reply to Kajal Karande

TI__Guru 55685 points

Hi Kajal,

Can you grep for L2CFG in csl folder.
There are APIs defined in <pdk>\packages\ti\csl\arch\c66x\dsp_icfg.h for L2 registers.

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

Hi,

I haven't heard back from you, I'm assuming you were able to resolve your issue.
If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

Regards,
Rishabh

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RTOS/TDA2: DSP: DDR and L2SRAM communication using edma