AM3352: RTC_PWRONRSTn specification

Hi,

For both questions, yes. Note A, after the figures states this:

  "RTC_PWRONRSTn should be asserted for at least 1 ms to provide enough time for the internal RTC LDO output to reach a valid level before RTC reset is released".

As for the following statemnt:
 "- There is no dependency other powers and signals(1.8V Supplies,VDD_CORE,etc.) for RTC_PWRONRSTn release timing."

You should follow the sequence provided in the figures in datasheet. In figure Figure 6-2, for example, you can clearly see that the reset is released after PMIC_POWER_EN, 1.8-V Supplies & VDDS_DDR. You should comply with this.  Same with figure 6-3 & 6-4, you should comply with the described sequencing.

Best Regards,

Yordan

Hi Yordan,

Thank you for your reply.

I found the notes in the Figure 6-2/6-3/6-4 are described as follows.
"VDDS_RTC can be ramped independent of other power supplies if PMIC_POWER_EN functionality is not required. If
VDDS_RTC is ramped after VDD_CORE, there might be a small amount of additional leakage current on
VDD_CORE. The power sequence shown provides the lowest leakage option."

Please let me make sure again if my understanding in the following is correct.
I understanding as follows.
- RTC_PWRONRSTn must be LOW for at least 1ms after VDDS_RTC supplied.
- PMIC_POWER_EN will be HIGH after VDDS_RTC supplied. (PMIC_POWER_EN is AM3352 output signal.)
- Sequencing for VDDS_RTC and RTC_PWRONRSTn can be independent of other power supplies and signals.
(But, there might be a small amount of additional leakage current on VDD_CORE.)
- RTC_PWRONRSTn must be LOW for at least 1ms to reset the RTC domain.

Are these correct?

Regards,
Yasun

Hi Yordan,

Thank you for your reply.
My question became clear. Thank you very much.

Regards,
Yasun