RTOS/OMAP-L138: McBsp does not receive data from other processor

Hi Ramesh,

Are you using Processor SDK? And is your application based on the McBSP example provided in the SDK?

Are you using EDMA to service the McBSP?

Can you please provide a register dump of the SPCR?

Also, please ensure you are setting RRST bit to 1, followed by the FRST bit.

Hi Sachin,

Thanks for the reply. I'm Using the Quick start OMAPL138 example and customized to enable McBSP functionality via Mux. Yes the software uses edma to service mcbsp.

Yes, McBSP registers are configured and while starting the McBSP enabled the RRST bit.

Please find SPCR register screenshot in the attachment.

Thanks,

Ramesh G.

Hi Ramesh,

I am sorry for the delayed response here. Can you provide a register dump of the McBSP register? If you can zip up your project and attach it here or send it over email so that we can take a closer look, that would be even better.

Edit: I'm also looping in the HW engineer to rule out any issues with the hardware.

Hi Sahin,

Thanks for the response. Configured McBSP0 to receive the data from other processor (Verified in scope that other processor transmits FSR, CLK, Data) but It appears that the software doesn't receive the complete data (partial or incomplete data in FIFO and rx ping/pong buffers ) with RFIFOCTL or DRR options (with disabling the Fifo option) and observing that McBSP SPCR (RFULL is 1)

Please find the McBSP0 register , intr, edma paramset, and other config info below:-

interrupt:INTR4 ISR  enabled for CSL_INTC_EVENTID_EDMA3_0_CC0_INT1 (8)

hMcbsp0Fifo->RFIFOCTL (RNUMDMA = 1 words)

hMcbsp0Fifo->RFIFOCTL (RNUMEVT = 64 words)
hMcbsp0Fifo->RFIFOCTL (RENA = ENABLED) (Disabled to read directly from DRR)

hMcbsp0->SPCR (RRST = ENABLE)

DRA[1].DRAE = 0x00003C3Fu; //Enable DMA Channels 0-5, 10-13 to Shadow Region 1
edma3_0cc0Regs->IESR = 0x00000C0C; //Enable TCC Interrupts for Channels 2,3,10,11
edma3_0cc0Regs->EESR = 0x0000000C; //Enable McBSP0 Events 2,3

//McBSP0 Rx Ping PaRAM Set
CSL_Edma3ccParamSetRegs PaRAMSetMCBSP0RxPing = {
(0x00102000), // TCC = 2
(Uint32)0x01F10000, // McBSP0 FIFO Data or DRR 0x01D10000
(0x00010400), //MSB BCT = 16 and 0x400 * 32bits
(Uint32)mcbsp0_rx_ping, // Ping Buffer
( 0x04000000), // DSTBIDX=ACNT, SRCBIDX=0
(0x00100E60), // BCNTRLD = 16(bcnt) and Link to Rx Pong Parameter Set - PaRAMSetMCBSP0RxPong
(0 | 0),
(1) //CNT
};

//McBSP0 Rx Pong PaRAM Set
CSL_Edma3ccParamSetRegs PaRAMSetMCBSP0RxPong = {
(0x0010A000), // TCC = 10
(Uint32)0x01F10000, // McBSP0 FIFO Data or DRR 0x01D10000
(0x00010400), //MSB BCT = 16 and 0x400 * 32bits
(Uint32)mcbsp0_rx_pong, // Ping Buffer
(0x04000000), // DSTBIDX=ACNT, SRCBIDX=0
(0x00100E40), // BCNTRLD = 16(bcnt) and link to Rx Ping Parameter Set - PaRAMSetMCBSP0RxPing
(0 | 0), // DSTCIDX=ACNT*BCNT, SRCCIDX=0
(1) //CNT
};

TCC=2 for Rx Ping

TCC=10 for Rx Pong

PARAMSET[2] = PaRAMSetMCBSP0RxPing;

PARAMSET[114] = PaRAMSetMCBSP0RxPing;

PARAMSET[115] = PaRAMSetMCBSP0RxPong;

. 

Hi Sahin,

I am sorry for the delayed response, we could able to receive the data when we configured to McBSP1 (U22 chip) looks like some problem in the U23 chip.

We would like to the receive McBSP data and write into SATA drive. I dont see much driver example on DSP Side for SATA drive. So planning to use OMAP L138 ARM (A9) processor to read McBSP data and write into SATA instead of DSP processor .

Does OMAP L138 ARM(A9) Supports McBSP peripheral interface?. If ARM supports McBSP peripheral interface then Could you please provide McBSP/SATA driver example path?

Thanks,
Ramesh G.

Hi Ramesh,

It is possible that U23 is causing the McBSP0 signals to be in contention, but the I wouldn't expect any contention from its input pins that are shared with CLKR0 and FSR0.

How did you make the board mod to connect another device to McBSP0?
Make sure you short GND between the two devices so they have a common reference.

Tracing these three McBSP0 signals on the LCDK EVM...
* MCBSP0_CLKR0 --> AXR6/MII_TXEN --> TXEN - VIS (PD) Variable voltage Schmitt-triggered input --> should not be affected by U3

* MCBSP0_FSR0 --> AXR2/MII_TXD2 --> TXD2 - VIS Variable voltage Schmitt-triggered input --> should not be affected by U3

* MCBSP0_DR0 --> SPI0_SIMO/EPWM0_SYN --> COL/CRS_DV/MODE2 - VIS (PD) or VO8 Variable voltage Schmitt-triggered input or Variable voltage output with 8mA sink and 8mA source --> Could be in contention with U23, but should only corrupt data instead of hanging the McBSP.

How are the rest of the McBSP0 signals pin muxed?

=-=-
You can try to remove the whole U23 from the system by asserting its reset, but that would also reset the CDCM device needed for SATA...
Asserting PHP_RSTn low (by shorting J15 header pin 18 to pin 22 or P1 pin 18 to pin 22)
will keep the following devices in reset...

U23 LAN8710A-EZK
U9 CDCM61001RHBT - needed for SATA!
U21 TVP5147M1PFP
U22 TLV320AIC3106IRGZ

Its a worthy test to see if you can get McBSP0 to receive data from your other device.

Unfortunately, you cannot lift a pin on the U23 device because of its QFN package.
If U23 floats its pins when held in reset and the above test works, you may be able to cut the trace to pin 19 nRST, and pull or tie it low (I havent checked the layout to see if its possible)

You may also be able to cut the traces for AXR6/MII_TXEN and AXR2/MII_TXD2 to isolate them from U23. To isolate SPI0_SIMO/EPWM0_SYN, you only have to remove R183.

Not sure I offered much help... Good luck.

Regards,
Mark

Hi Mark, Thanks for the detailed response. U22/U23 both pins Receiving Data, Clock, Frame Sync pins are connected to another processor 5509A Transmit data, clock and sync pins for McBSP0 and McBSP1. For McBSP1 configuration we are able to receive the data successfully.

I believe we are good with data receiving portion. My requirement is reading data via McBSP and writing it to SATA for this requirement , I dont think DSP processor is the right choice because DSP purpose is different. Please suggest low cost processor which supports McBSP and SATA interface.

Thanks,
Ramesh G.

Thanks Mark and sorry for the late response. We are considering AM1808 (ARM9) processor but having few questions on the McBSP/SATA peripherals. 

1. Where can I find McBSP/SATA (Linux side) driver example software for AM1808 OMAP-L138.

2. We have developed McBSP driver for DSP side. Since we are moving to AM1808 (ARM9) processor just wanted to modify the McBSP driver and use it on ARM side. In order to compile McBSP driver on linux side we need to know the compilation process/steps/procedure on linux side. 

Thanks,

Ramesh G.

 

Hi Ramesh,

Working on answers to these questions.

Regarding the SATA driver... Linux SATA driver is open source software TI takes from upstream Linux code. It is located in linux/drivers/ata.
There isn’t any example software. SATA Gen2 is supported and tested on OMAP-L138.

Regards,
Mark

Thanks Mark for the response. Having few more queries on AM1808 or other processor side. AM1808 processor meets our requirement (i.e. McBSP and SATA) but does the McBSP is supported by default in AM1808 linux kernel, if so where can I find examples demonstrating AM1808 McBSP with linux kernel, otherwise please suggest any processor which supports McBSP and SATA with linux kernel.

We have OMAP L138 DSP(6748) McBSP working application driver software. Can I modify the DSP working McBSP software as per ARM and use it as Application driver on ARM side?. If so will Linux Kernel allow McBSP Application driver to interact with McBSP without any issues? or will linux kernel blocks (Memory, permission, hardware/peripheral interactions) anything while ARM application driver interacts with McBSP?.

Please advise.

Thanks,
Ramesh G.