RTOS/66AK2G12: How to declare K2G MSMC to be non-cacheable from within DSP?

Sagar Sadasivan

Prodigy 205 points

Part Number: 66AK2G12
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Customer Question:

We have the following configuration:

K2G12 processor with DDR3L SDRAM

Both ARM and DSP under TI-RTOS with the following versions

bios_6_46_05_55

CCS Version: 7.2.0.00013

pdk_k2g_1_0_7

processor_sdk_rtos_k2g_4_01_00_06

We would like to declare K2G MSMC to be non-cacheable for both ARM and DSP. The address of MSMC starts from 0x0c000000. The size is 1MB.

We are able to declare K2G MSMC to be non-cacheable from ARM perspective but not DSP.

Refer to the link below

https://e2e.ti.com/support/processors/f/791/t/718619?tisearch=e2e-quicksearch&keymatch=disable cache MSMC

We disable cache on DSP in .cfg file like below:

var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');

// Cache.setMarMeta(base_address, length, Cache.Mar_DISABLE)

Cache.setMarMeta(0x0C000000, 0x00100000, Cache.Mar_DISABLE);

But we still need to call CacheP_wbInv() in order to update DSP data correctly.

How to declare K2G MSMC to be non-cacheable from DSP perspective?"

over 6 years ago

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Hi Sagar,

Sorry, but I am kind of confused. The use of:
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.setMarMeta(0x0C000000, 0x00100000, Cache.Mar_DISABLE);

makes the 1MB of MSMC non-cacheable. Isn't this the case in your application?

Best Regards,
Yordan

0 Sagar Sadasivan over 6 years ago in reply to Yordan Kovachev

TI__Prodigy 205 points

"Yes, we want to makes the 1MB of MSMC non-cacheable. Our K2G ARM core also accesses MSMC. Our DSP L1 memory is used for cache. DSP L2 memory is for internal SRAM memory to store program and data.
We want whenever DSP reads or writes data to MSMC it will get updated right away instead of getting data from L1 memory. But we don’t always get data correctly if we don’t call CacheP_wbInv()
before access MSMC. I shouldn’t need to call CacheP_wbInv() if I setup MSMC non-cacheable correctly. Is there any steps I missed to proper set up MSMC non-cacheable?"

0 lding over 6 years ago in reply to Sagar Sadasivan

TI__Guru* 95265 points

Hi,

Check the C66x DSP corepac user guide:

7.3.2.2.2 MSMC RAM Aliasing Scenarios
C66x CorePac’s MARs only allows configuring the cacheability of 16MB ranges. It also
hardwires the cacheability of certain address ranges, such as the range that corresponds
to MSMC RAM. Using MPAX segments, programs can provide multiple aliases of
various address ranges in the C66x CorePac’s 32-bit address space. The L2 controller
treats accesses to these aliases as cacheable or non-cacheable based on the setting of the
corresponding MAR register bits.
Thus, the cacheability of each alias can be controlled independently. This even applies
to MSMC RAM: By making an alias of MSMC RAM at some other address, its
cacheability becomes controlled by the corresponding MAR bits as well, rather than the
default semantic applied to MSMC RAM when accessed at 0C00_0000 – 0C1F_FFFF.

See Table 7-6 MSMC RAM Aliasing Scenarios.

You need to use MPAX to map MSMC to another address range to control the cache.

Regards, Eric

0 Sagar Sadasivan over 6 years ago in reply to lding

TI__Prodigy 205 points

"I would like to do it right.

Can you give me an example to use MPAX to map MSMC to another address range to control the cache in .cfg file? Thanks."

0 lding over 6 years ago in reply to Sagar Sadasivan

TI__Guru* 95265 points

Hi,

This is typically done by CSL level code. You may refer to: processors.wiki.ti.com/.../MemoryProtectionOnKeystoneDevices
At the end there is:
Appendix A. Example code
The Example Code can be downloaded from here:

MemoryProtectionExample.zip

You can see MPAX setup code inside.

Also, you can refer to pdk_k2g_1_0_x\packages\ti\csl\example\xmc_mpu.

Regards, Eric

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RTOS/66AK2G12: How to declare K2G MSMC to be non-cacheable from within DSP?