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UPP DMA Starts Early

Dave Chen
Prodigy 50 points

I am setting up the UPP DMAs on both channels in Receive mode, using Enable active low.  The Clock is only active during the burst of valid data, and then 32 additional clocks after the burst. After an incomplete DMA of 4 lines of 16 KBytes on each channel, I reset and try again.  From that point on, the DMA moves some amount of data, in most cases 512 bytes, prior to any data on the interface.

Does the UPP input require a continuous clock in order to operate properly?

If the DMA is programmed for 64 KBytes and there are exactly 64 KBytes input, bracketed by Enable, does the DMA move all 64 KBytes, or does some data get stuck in the UPP input FIFOs until the next DMA?

Does UPP Reset clear these UPP input FIFOs?

 

 

 

  • 0
    Prodigy 50 points

    With an incrementing count coming in the data bus, I notice 3 samples are missing at the beginning of the buffer.  The DMA was set up to ignore Start and Enable in this case. It is as if there must be several UPP_CLK cycles before the first valid data, or else the first few data samples will be lost.

    My UPP_CLK is normally logic 1. The UPP interface seems to think there are valid clocks unless I configure the interface to invert the clock using the CLKINV bits in the ICR register.

     

  • 0 in reply to Dave Chen
    TI__Expert 8890 points

    Dave,

    I will try to answer your questions in order.

    1. It should not be necessary to provide a continuous clock signal to the uPP when it is inactive in receive mode.  However, it's worth noting that the uPP in transmit mode does always output an active clock signal, even when no transactions are currently in progress.  If you are having trouble with the uPP in receive mode, it may be a good idea to try a continuous input clock.  (But I don't think it should be necessary.)
    2. When a transfer completes, the DMA should move all of the data immediately to (or from) the data buffer in memory.  However, I believe that the end-of-window interrupt occurs when the final DMA burst starts, not when it completes.  The time difference between the start and end of that burst should be very small, but it's something to be aware of.
    3. Placing the uPP peripheral in reset should clear all of the internal FIFOs.
    4. The clock signal should be left in the "off" state when it's not being driven.  By default, this would be low (0).  You can invert the clock to make it inactive high (1).

    Hope this helps.

  • 0 in reply to Joe Coombs
    Prodigy 50 points

    Thank you Joe. This helps.  Especially item 4.  The UPP interface behaves unexpectedly unless I configure the clock to be inverted.