AM5716: AMMU configuration to L3/L4 peripheral bus for posted write

Kzk

Part Number: AM5716

Hi Experts,

I'd like IPU0 (Cortex-M4) to write the registers in L3/4 peripheral bus at high speed and low latency with the posted write. In order to realize this, I think I need to configure AMMU and Cache. How can I set CACHE_MMU_xxx_POLICY_i register or something for L3/4 peripheral area? In my application, IPU0 has to access GPIO, GPMC and etc fast. Please give me some advice.

Regards,
Kzk

over 6 years ago

0 Garrett Ding over 6 years ago

TI__Mastermind 43296 points

Hi Kzk,

You may refer to the example .cfg file for IPU AMMU and cache configuration - pdk\packages\ti\drv\gpio\test\led_blink\am571x\m4\bios\gpio_m4_idkAM571x.cfg

Regards,
Garrett

0 Kzk over 6 years ago in reply to Garrett Ding

Genius 5785 points

Hi Garrett,

Garrett Ding said:
You may refer to the example .cfg file for IPU AMMU and cache configuration - pdk\packages\ti\drv\gpio\test\led_blink\am571x\m4\bios\gpio_m4_idkAM571x.cfg

Thank you for your reply. It looks like that L4 is configured by Large[0] and Large[3]. For example, "AMMU.PostedPolicy_NON_POSTED" is set in the configuration. Is the L4 registers writing efficiently with this setting? When I change it to "POSTED", the latency is the same. Is there a possibility that it can be made faster by changing something with these settings?

I'm using PDK v1.0.10 of PSDK-RTOS v4.3.

/* Large PAGE */
AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[0].logicalAddress = 0x40000000;
AMMU.largePages[0].translatedAddress = 0x40000000;
AMMU.largePages[0].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[0].size = AMMU.Large_512M;
AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.largePages[0].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[0].L2_posted = AMMU.PostedPolicy_NON_POSTED;

AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
AMMU.largePages[3].logicalAddress = 0x60000000;
AMMU.largePages[3].translatedAddress = 0x40000000;
AMMU.largePages[3].translationEnabled = AMMU.Enable_YES;
AMMU.largePages[3].size = AMMU.Large_512M;
AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_NON_POSTED;
AMMU.largePages[3].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
AMMU.largePages[3].L2_posted = AMMU.PostedPolicy_NON_POSTED;

Regards,

Kzk

0 Kzk over 6 years ago in reply to Kzk

Genius 5785 points

Hi Garrett,

I refer to GEL and set the policy register for L4_WKUP(GPIO1) to 0x00200007, the time for the write access to GPIO1 has been reduced to 1/3. Could you give me some advice on this result?

C:\ti\ccsv8\ccs_base\emulation\boards\am571x\gel\AM571x_multicore_reset.gel

/*Medium Page*/
regAddr = IPU_MMU_CFG;
regAddr += 0x860;
WR_MEM_32(regAddr, 0x00300000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x4AE00000); regAddr += 0x4;/* L4_WKUP Logical Address */

regAddr = IPU_MMU_CFG;
regAddr += 0x8A0;
WR_MEM_32(regAddr, 0x40300000); regAddr += 0x4;
WR_MEM_32(regAddr, 0x4AE00000); regAddr += 0x4;/* L4_WKUP Physical Address */

regAddr = IPU_MMU_CFG;
regAddr += 0x8E0;
WR_MEM_32(regAddr, 0x00000007); regAddr += 0x4;
WR_MEM_32(regAddr, 0x00020007); regAddr += 0x4;/* L4_WKUP Policy=Posted, Non-cacheable */

Regards,

Kzk

0 Garrett Ding over 6 years ago in reply to Kzk

TI__Mastermind 43296 points

Hi Kzk,

The policy value 0x00200007 indicates posted and non-cacheable, but in your previous post you also mentioned the latency is the same when changing the policy to 'POSTED', could you clarify it? Also how much latency with 'POSTED' and 'Non-posted' do you observe?

Thanks,
Garrett

0 Kzk over 6 years ago in reply to Garrett Ding

Genius 5785 points

Hi Garrett,

I'm sorry that the explaination is difficult to understand. Also, my test was wrong in my previous post. I attached the environment that I checked the operation. Could you please check that?

First, copy main.c below and build it.
C:\ti\pdk_am57xx_1_0_10\packages\ti\csl\example\gpio\gpio_toggle

Then, execute the program with IPU on IDK5718. Since calling UNICACHEEnable in main.c, the program on DDR3 is cached. LED1 blinks blue at short intervals. This is due to a process in the delay function. LED2 blinks green at 5 second intervals. Terminate the CCS Debug Perspective once.

After that, copy the gel files below. Create a new Target Configuration File with AM571x_cortexa15_cpu0_startup_TEST.gel as the initialization script of Cortex-A15.
C:\ti\ccsv8\ccs_base\emulation\boards\am571x\gel

Finally, re-launch the CCS Debug Perspective with the new configuration above and execute the program. Since L4_WKUP for GPIO1 is set to Posted setting in AM571x_multicore_reset_TEST.gel, the blinking interval of LED2 (green) is earlier. I think so.

Regards,
Kzk

Fullscreen 2021.main.c Download

/*
 *  Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
 *
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 *  modification, are permitted provided that the following conditions
 *  are met:
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 *    notice, this list of conditions and the following disclaimer.
 *
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 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
 /**
 *  \file   main.c
 *
 *  \brief This file demonstrates toggling gpio pins high and low
 *         using GPIO dal API's.
 *
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "stdint.h"
#include <ti/csl/csl_gpio.h>
#if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_AM571x)
#include <ti/board/board.h>
#endif
#include <ti/csl/example/utils/uart_console/inc/uartConfig.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/arch/csl_arch.h>   // for calling Cache API

/* ========================================================================== */
/*                                 Macros                                     */
/* ========================================================================== */
/* None */

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
uint32_t gPinDirection = GPIO_DIR_OUTPUT;

/*To use UARTConfigPuts(uartBaseAddr, function for prints*/
/*To use UARTConfigPuts function for prints*/
#if (defined (SOC_AM574x) || defined (SOC_AM572x)) || (defined (SOC_AM571x))
uint32_t uartBaseAddr = CSL_MPU_UART3_REGS;
#endif
#if defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA75x)
uint32_t uartBaseAddr = SOC_UART1_BASE;
#endif
#if defined (SOC_TDA3XX) || defined (SOC_DRA78x)
uint32_t uartBaseAddr = SOC_UART3_BASE;
#endif

#if (defined (SOC_AM574x) || defined (SOC_AM572x)) || (defined (SOC_AM571x))
uint32_t gpio_base_address = CSL_MPU_GPIO7_REGS;
uint32_t gpio_pin          = 8;
uint32_t gpio_base_address2= CSL_MPU_GPIO1_REGS;    // LED1 for delay counter
uint32_t gpio_pin2         = 5;                     // LED1 for delay counter
#elif defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA75x)
uint32_t gpio_base_address = SOC_GPIO1_BASE;
uint32_t gpio_pin          = 14;
#elif defined (SOC_TDA3XX) || defined (SOC_DRA78x)
uint32_t gpio_base_address = SOC_GPIO4_BASE;
uint32_t gpio_pin          = 9;
#endif

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */
void padconfig_PrcmEnable()
{
#if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_AM571x)
    /*Pad configurations */
    Board_initCfg boardCfg;
    boardCfg = BOARD_INIT_UNLOCK_MMR | BOARD_INIT_UART_STDIO | 
               BOARD_INIT_MODULE_CLOCK | BOARD_INIT_PINMUX_CONFIG;
    Board_init(boardCfg);  

    HW_WR_REG32(CSL_MPU_CORE_PAD_IO_REGISTERS_REGS+CSL_CONTROL_CORE_PAD_IO_PAD_DCAN1_TX,0x0006000E);
    /*Enable GPIO clock*/
    HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG,0x102);
     while ((HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO2_CLKCTRL_REG) & (0x00030000U)) != 0x0)
        {
            ;
        }
    HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG,0x102);
     while ((HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO3_CLKCTRL_REG) & (0x00030000U)) != 0x0)
        {
            ;
        }
    HW_WR_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG,0x102);
    while ((HW_RD_REG32(CSL_MPU_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER_GPIO4_CLKCTRL_REG) & (0x00030000U)) != 0x0)
        {
            ;
        }
#endif
#if defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_TDA2EX) || defined (SOC_DRA72x) || defined (SOC_DRA75x)
    /*Pad configurations */
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_UART1_RXD,0x00040000);
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_UART1_TXD,0x00040000);
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_DCAN1_TX,0x0006000E);
    /*Enable GPIO clock*/
    HW_WR_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO2_CLKCTRL,0x102);
    while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
        {
            ;
        }
    HW_WR_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO3_CLKCTRL,0x102);
     while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO3_CLKCTRL) & (0x00030000U)) != 0x0)
        {
            ;
        }
    HW_WR_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO4_CLKCTRL,0x102);
    while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE+CM_L4PER_GPIO4_CLKCTRL) & (0x00030000U)) != 0x0)
        {
            ;
        }
    /* Set the UART Parameters */
    UARTConfigInit(uartBaseAddr, BAUD_RATE_115200, UART_WORD_LENGTH_8, UART_STOP_BIT_1, UART_NO_PARITY,
                   UART_16x_MODE);
#endif
#if defined (SOC_TDA3XX) || defined (SOC_DRA78x)
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_SCLK,0x00040001);
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_SPI1_CS0,0x00000001);
    HW_WR_REG32(SOC_CORE_PAD_IO_REGISTERS_BASE+CTRL_CORE_PAD_IO_DCAN1_TX,0x0006000E);
    /* Set the access to the GPMC registers - Enable GPMC Clock */
    HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO2_CLKCTRL, 0x102);
    while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +
                    CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
       {
            ;
       }
   HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO3_CLKCTRL, 0x102);
   while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +
                    CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
       {
            ;
       }
   HW_WR_REG32(SOC_L4PER_CM_CORE_BASE + CM_L4PER_GPIO4_CLKCTRL, 0x102);
   while ((HW_RD_REG32(SOC_L4PER_CM_CORE_BASE +
                    CM_L4PER_GPIO2_CLKCTRL) & (0x00030000U)) != 0x0)
       {
            ;
       }
    /* Set the UART Parameters */
    UARTConfigInit(uartBaseAddr, BAUD_RATE_115200, UART_WORD_LENGTH_8, UART_STOP_BIT_1, UART_NO_PARITY,
                   UART_16x_MODE);
#endif
}
void delay(void)
{
    volatile uint32_t i;
#if 0
    /* Original */
    for (i = 0; i < 4000000; i++)
    {}
#else
    for (i = 0; i < 4000000; i++) {
        GPIOPinWrite(gpio_base_address2, gpio_pin2, GPIO_PIN_HIGH);
        GPIOPinWrite(gpio_base_address2, gpio_pin2, GPIO_PIN_LOW);
    }
#endif
}

int main(void)
{
    volatile uint32_t checkOutput = 1;

    padconfig_PrcmEnable();
    
#if    defined (__TI_ARM_V7M4__)
    /* Enable AMMU for M4 */
    #if 0
    AppUtilsConfigIPU1DefaultAMMU();// configured by AM571x_multicore_reset_TEST.gel
    #endif
    /* Enable UniCache */
    UNICACHEEnable(CSL_IPU_IPU1_UNICACHE_MMU_CONF_REGS_REGS);
#endif

    UARTConfigPuts(uartBaseAddr,"\nGPIO Output App", -1);
    UARTConfigPuts(uartBaseAddr,"\nGenerating a square wave on GPIO pin", -1);
#if defined (SOC_AM574x) || defined (SOC_AM572x) || defined (SOC_TDA2XX) || defined (SOC_TDA2PX) || defined (SOC_DRA75x) || defined (SOC_AM571x) || defined (SOC_TDA2EX) || defined (SOC_DRA72x)
    UARTConfigPuts(uartBaseAddr,"\nProbe the GPIO1 pin 14 on JP2 connector - pin 1 on EVM", -1);
#elif defined (SOC_TDA3XX) || defined (SOC_DRA78x)
    UARTConfigPuts(uartBaseAddr,"\nProbe the GPIO4 pin 9 on J6108 connector - pin 1 on EVM", -1);
#endif

    GPIOModuleReset(gpio_base_address);
    GPIOModuleReset(gpio_base_address2);

    GPIOModuleEnable(gpio_base_address);
    GPIOModuleEnable(gpio_base_address2);

    GPIODirModeSet(gpio_base_address, gpio_pin, gPinDirection);
    GPIODirModeSet(gpio_base_address2,gpio_pin2,gPinDirection);

    while (checkOutput)
    {
        GPIOPinWrite(gpio_base_address, gpio_pin, GPIO_PIN_HIGH);
        delay();

        GPIOPinWrite(gpio_base_address, gpio_pin, GPIO_PIN_LOW);
        delay();
    }

    return 0;
}
/********************************* End of file ******************************/

AM571x_cortexa15_cpu0_startup_TEST.gel AM571x_multicore_reset_TEST.gel

0 Kzk over 6 years ago in reply to Kzk

Genius 5785 points

Hi Garrett,

Could you please confirm my software?

Regards,
Kzk

0 Garrett Ding over 6 years ago in reply to Kzk

TI__Mastermind 43296 points

Kzk,

You probably can try to port the medium page policy for L4_WAKEUP 256KB from the gel file to .cfg file, that may take effect as well.

The GPIO1 starting from 0x4AE1_0000 is covered in the medium page of L4_WAKUP starting from 0x4AE0_0000, that may explain why the POST write works as expected with the AMMU policy defined in gel file.

Regards,
Garrett

0 Kzk over 6 years ago in reply to Garrett Ding

Genius 5785 points

Hi Garrett,

Thank you for checking the effect of the "posted" configuration. I'll implement it in the program.

Regards,
Kzk

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AM5716: AMMU configuration to L3/L4 peripheral bus for posted write