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AM5748: SATA Controller Port Reset method

Daisuke Maeda
Guru 20205 points
Part Number: AM5748

Our customer is confused about how to wait for re-establishment of communication after clearing PxSCTL.DET to 0h.

In the AHCI specification revision 1.1:
"After  clearing  PxSCTL.DET  to  0h,  software  should  wait  for communication to be re-established as indicated by bit 0 of PxSSTS.DET being set to ‘1’."

https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1_1.pdf

In the AHCI specification revision 1.3.1:
"After  clearing  PxSCTL.DET  to  0h,  software  should  wait  for communication to be re-established as indicated by PxSSTS.DET being set to 3h."

https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/serial-ata-ahci-spec-rev1-3-1.pdf

From the register description:
"Read 0x1: Device presence detected but PHY communication not established"
"Read 0x3: Device presence detected and PHY communication established"

If PxSSTS.DET is set to 3h, that indicates the re-establishment of the communication, but if bit 0 of PxSSTS.DET is set to 1b, that may not.

Should it wait for PxSSTS.DET to be set to 3h after clearing PxSCTL.DET to 0h?

Best regards,

Daisuke