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Linux/AM3352: LCD Controller running in Standby Mode

Stephan BAW
Prodigy 130 points
Part Number: AM3352

Tool/software: Linux

Hi there

We have a custom Board with an LCD, based on AM3352 running linux.

For power consumption optimization we will use the predefined standby Mode in linux

"echo standby > /sys/power/state" which will stops the A8 Core and the M3 will listen to the wakeup sources and resume the A8 on an event.

We need to display an image on the LCD during standby.

I got the LCD Subsystem running again, by patching the M3 Firmware and enabling there in the CM_PER Register the LCD Clocks (0x44e00018 and 0x44e00148)

This leads to a running Pixel Clock, Hsync and Vsync Pulses.

Unfortunately no data is present on the LCD_Data[x] Pins.

Is there any possibility to get data Displayed through the LCD DMA in Standby?

I also tried to switch the DMA Base and Ceiling of the LCD Controller to some Registers accessilbe by the M3, which can be modified by JTAG. But also with present and accessible Data from the M3, no Data is outputed on the LCD_Data Pins.

We like to display the last Image in the framebuffer.

Do we need to prevent the DDR3 from self retention mode to deliver data to the LCD DMA?

Basically I'm interrested if its possible to get the LCD subsystem running in standby mode and output an image on the LCD.

Many thanks for your response.

  • 0
    TI__Guru** 101060 points
    Hello,

    What version of Linux are you running?

    Regards,
    Nick
  • 0 in reply to Nick Saulnier
    Prodigy 130 points
    Hello Nick

    We are running Yocto (sumo) with a few patches for the Kernel and our devicetree.
    The kernel is version 4.14 based on meta-ti.

    Best Regards
    Stephan
  • 0 in reply to Stephan BAW
    TI__Mastermind 22946 points
    Hi Stephan,

    This is a non-supported feature by us. Unless we go through the implementation steps ourselves, hard to comment on feasibility of the use case and the resolution for the issue you are seeing. Since this is a non-supported feature, we do not plan to attempt the use case at our side. Sorry.

    Regards,
    Manisha
  • 0 in reply to Manisha Agrawal
    Prodigy 130 points
    Hi Manisha

    I'm just wondering if it is possible by the hardware or not.

    I got just everything working except of the data output.

    Probably a further clock needs to be enabled ...

    It would be very helpfull if you could check the hardware capability or if you could provide me a connection diagram of the LCD controller and its DMA.

    I would like to understand, which path through the SoC is taken for the data and which clocks and plls are needed for that.

    Many thanks for our reply.
    Best regards
    Stephan
  • 0 in reply to Stephan BAW
    TI__Mastermind 22946 points
    Hi Stephen,

    Running the LCDC while Linux is in suspend mode is doable as long as M3 enables everything required. So from hardware perspective this is doable.

    If you have JTAG connection, may be you can get a LCDC register dump when Linux is running and when in suspend mode and compare the register settings.

    Memory also need to function in suspend mode as LCDC need to fetch the pixels. So you may also need to check on that part.

    You might also want to check the pinmuxing as that might also be changed to safe-mode at suspend.

    I will try to see if I can response to other two specific queries that you asked.

    Regards,
    Manisha
  • 0 in reply to Manisha Agrawal
    Prodigy 130 points

    Hi Manisha

    Many thanks, this are very good news.

    Could you already find some more information ?

    Best regards

    Stephan

  • 0 in reply to Stephan BAW
    TI__Guru* 83885 points
    Hi Stephan
    Looks like we never got back to you on this thread. Apologies for that.
    Are you still looking for additional information on this? Have you looked at the TRM and not found specific information?

    Please let us know
    Regards
    Mukul
  • 0 in reply to Mukul Bhatnagar
    Prodigy 130 points
    Hi Mukul
    I am still looking for the issue, why no data is outputted by the DMA. PCLK, HSYNC, VSYNC are present. I think something is not yet enabled in DMA context.
    If you could provide me an idea of the dataflow path from RAM to the LCD Controller, with all gates and clocks needed, you would help me a lot.
    I could't find this explicit information in the TRM. I found only the general description in Chapter 13.1.1

    Many thanks for your reply
    Best regards
    Stephan
  • 0 in reply to Stephan BAW
    TI__Mastermind 23125 points
    Stephan,
    The thread was forwarded to me yesterday. To understand what experiment you've done so far - did you confirm if the DDR is in self-refresh during the Standby power state? I assume you last frame buffer is sitting in the DDR, then you would need the DDR to be in active mode as well as L3 interconnect.
    let us know if there is no easy ways for your to check. I can ping the Linux team to get details on how Standby is implemented in the SDK.
    regards
    Jian