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Linux: am335x-evm-linux-sdk-arago-src-03.03.00.04(linux Kernel 4.4.41)

Other Parts Discussed in Thread: TL16C550C

Tool/software: Linux

dear  Sir:

   我们使用了,SDK 03.03.00.04, 使用的芯片是3352, 定制了一块核心板,增加扩展芯片CH438(1扩8串口) ,目前的串口使用的和NAND flash  共同使用 GPMC ,NAND FLASH 使用 CS0 ,CH438 使用CS1

芯片CH438脚  ALE 接到GPMC ALE 上。(linux  Kernel 4.4.41)

在GPMC  中打算使用(C14) EMU0.gpio3[7] 作为共享中断使用 请帮忙份分析一下,对应的DTS 该如何配置。

1. DTS 中 (C14) EMU0.gpio3[7] 该如何配置。

     interrupt-parent =;
     interrupts =    

    配置的对应TI 3352关系是如何

2. DTS 中 对应的   

reg = <1 0x20 8>;  这一块,第二位的0X20 和GPMC 的对应关系如何。

BR !

guanyun

  • Hi,

    Please post in English, so that we can understand your question.

    Best Regards,
    Yordan
  • Yordan,

    We used SDK 03.03.00.04. The chip used is 3352. We customized a core board and added CH438 (1 extended 8 serial port). The current serial port uses GPMC together with NAND flash, NAND FLASH uses CS0, CH438 uses CS1.

    Chip CH438 foot ALE is connected to GPMC ALE. (linux Kernel 4.4.41)

    In GPMC, we intend to use (C14) EMU0.gpio3[7] as CH438 shared interrupt. Please help us to analyze how to configure the corresponding DTS.

    BR !

    guan yun

  • Hi,

    I am not familiar with the CH438. However, to see how you can use both CS0 & CS1 of the GPMC you can take a look at the kernel documentation:
    Documentation/devictree/bindings/mtd/gpmc-nand.txt

    Also look at these E2Es:
    e2e.ti.com/.../1530903
    e2e.ti.com/.../343017

    Best Regards,
    Yordan
  • Yordan,
    Thank you for your reply.

    I looked at it and didn't understand how to calculate the device's access address. hypothesis

    How does a device access the address of a device under the GPMC bus

    00H-07H is the register of device 0, 10H-17H is device 1, 18H-1FH is device 2, 20H-27H is device 2.

    The ALE signal controls how to calculate the device address under the data bus latch address.

    Please help with the analysis.

            gpmc: gpmc@50000000 {
                compatible = "ti,am3352-gpmc";
                ti,hwmods = "gpmc";
                ti,no-idle-on-init;
                reg = <0x50000000 0x2000>;
                interrupts = <100>;
                dmas = <&edma 52 0>;
                dma-names = "rxtx";
                gpmc,num-cs = <7>;
                gpmc,num-waitpins = <2>;
                #address-cells = <2>;
                #size-cells = <1>;
                interrupt-controller;
                #interrupt-cells = <2>;
                gpio-controller;
                #gpio-cells = <2>;

        pinctrl-names = "default", "sleep";

        ranges = <0 0 0x08000000 0x1000000>,/* CS0: 16MB for NAND */
         <1 0 0x09000000 0x01000000>;/* CS1:  for duart */        
        duart@1,0 {
        compatible = "mrvl,mmp-uart";
        reg = <1 ? 8>;/* CS1, offset 0, IO size 8 */
        interrupt-parent = <&gpio?>;
        interrupts = <? 8>;  /* gpio103 */
            };
        };
    Regards,
    Guanyun

  • Yordan
    I consulted CH438 and TL16C550C are compatible chips if it is TL16C550C.
    Regards,
    Guanyun
  • Hi,

    How does a device access the address of a device under the GPMC bus

    The processor accesses the given CS address space. In your case:
    ranges = <0 0 0x08000000 0x1000000>,/* CS0: 16MB for NAND */
    <1 0 0x09000000 0x01000000>;/* CS1: for duart */

    0x08000000 --> start address for NAND on CS0
    0x09000000 --> start address for DUART on CS1

    Best Regards,
    Yordan