Other Parts Discussed in Thread: SN74AHC1G09,
I use 96MBytes Nor Flash by CS2,CS3,CS5.
Is "the hardware connect" below OK?
Thank you very much!
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I use 96MBytes Nor Flash by CS2,CS3,CS5.
Is "the hardware connect" below OK?
Thank you very much!
Hi,
Chip selects are active low signals, and only one chip select can go low at a time.
The circuit you have drawn works with those assumptions. When any CS5, CS3, CS2 are selected CE on the Nor goes low and you can address with A25:A24 = 00, 01, 10 by accessing from the different chip selects.
Consider transients like power on and power down. I might go with an open drain output and external pull-up so the signals go down with the power supply.
http://www.ti.com/product/SN74AHC1G09
Regards,
Mark
cherry said:Mark Mckeown, Thanks for your reply!
When any CS5, CS3, CS2 are selected CE on the Nor goes low and I can address with A25:A24 = 00, 01, 11 by accessing from the different chip selects?
Thank you very much!
Is it deliberate that you have a discontinuity in the memory map from both the OMAP-L138 perspective as well as the NOR flash? In other words, because you never create A25:A24 = 10, you end up with a hole in the memory map. How will your NOR flash handle those accesses (or is that how it is supposed to be)?
It will also create a hole in the memory map from the OMAP-L138 side. Specifically your first 64MB of NOR flash will span 0x60000000-0x63FFFFFF. Then you'll have a hole and the final 32MB will span 0x66000000-0x67FFFFFF. Is that intentional? If you switch to CS4 that would alleviate the hole as viewed from the OMAP-L138. You would need to change your logic in order to eliminate the hole as viewed from the NOR flash.
If you would like the full 96M to be contiguous (from both sides of the bus), I recommend looking at this topology:
Best regards,
Brad