CCS/AM5728: DSP cache problem

Hi, Eric
First thanks for your reply.
Your question 1: With DDR cached and DDR non-cached, the number are exactly the same?

Yes, the cycles consumption report is same.

Your question 2: Is that possible the benefit you got using cache is overshadowed by the cache operation, so you didn't see any improvement?

Yes.

I think that the cache operation would not run for my code.

Please tell me, how to speed up the accessing DDR using cache.

Thanks again.

Regards.

Aither.

Hi, Eric.

First, thanks for your reply.

Please tell me that when the cache is ON, does the EDMA hardware automatically start between L2CACHE and DDR?

And, when CPU access the data on DDR, does the EDMA automatically transfer the data between L2CACHE and DDR without CPU operation or instruction?

Thanks again.

Regards.

Aither.

Hi, Eric
First, thanks for your effort and reply.
I tested DDR cache as bellow at AM5728 IDK:

main.c:

#define TEST_BUFF_SZ 8*1024*1024
#pragma DATA_ALIGN(a, CACHE_L2_LINESIZE)
#pragma DATA_ALIGN(b, CACHE_L2_LINESIZE)
#pragma DATA_ALIGN(c, CACHE_L2_LINESIZE)

#pragma DATA_SECTION(ppin, ".ddr")
#pragma DATA_SECTION(ppgradx_opt, ".ddr")
#pragma DATA_SECTION(ppgrady_opt, ".ddr")
#pragma DATA_SECTION(ppgradx_cn, ".ddr")
#pragma DATA_SECTION(ppgrady_cn, ".ddr")
static short a[TEST_BUFF_SZ], b[TEST_BUFF_SZ], c[TEST_BUFF_SZ];

int main ()
{
	int i, j ;
	clock_t t_start, t_stop, t_overhead, t_opt, t_i, t_cn;

#ifndef IO_CONSOLE
	Board_initCfg boardCfg;
#if defined(SOC_K2E) || defined(SOC_C6678)|| defined(SOC_K2H)|| defined(SOC_C6657)
	boardCfg = BOARD_INIT_MODULE_CLOCK |
	BOARD_INIT_UART_STDIO;
#else
	boardCfg = BOARD_INIT_PINMUX_CONFIG |
	BOARD_INIT_MODULE_CLOCK |
	BOARD_INIT_UART_STDIO;
#endif
	Board_init(boardCfg);
#endif

	for (i = 0; i < TEST_BUFF_SZ; i++)
	{
		a[i] = b[i] = i << 2;
	}
	
	TSCL= 0,TSCH=0;
	/* Compute the overhead of calling _itoll(TSCH, TSCL) twice to get timing info */
	/* ---------------------------------------------------------------- */
	t_start = _itoll(TSCH, TSCL);
	t_stop = _itoll(TSCH, TSCL);
	t_overhead = t_stop - t_start;

	t_start = _itoll(TSCH, TSCL);
	for (i = 0; i < TEST_BUFF_SZ; i++)
	{
		c[i] = a[i] + b[i];
	}

	t_stop = _itoll(TSCH, TSCL);
	t_cn = (t_stop - t_start) - t_overhead;
	printf("test1:%d,%d\n", t_cn, c[1]);

	CACHE_setL1PSize(CACHE_L1_32KCACHE);
	CACHE_setL1DSize(CACHE_L1_32KCACHE);
	CACHE_setL2Size(CACHE_128KCACHE); //USer defined.

	CACHE_enableCaching(64);
	CACHE_enableCaching(128);
	CACHE_enableCaching(129);

	CACHE_invL2((void *)0, 128*1024, CACHE_WAIT);
	CACHE_invL2Wait();

	for (i = 0; i < TEST_BUFF_SZ; i++)
	{
		a[i] = b[i] = i << 2;
	}
	TSCL= 0,TSCH=0;
	/* Compute the overhead of calling _itoll(TSCH, TSCL) twice to get timing info */
	/* ---------------------------------------------------------------- */
	t_start = _itoll(TSCH, TSCL);
	t_stop = _itoll(TSCH, TSCL);
	t_overhead = t_stop - t_start;

	t_start = _itoll(TSCH, TSCL);
	for (i = 0; i < TEST_BUFF_SZ; i++)
	{
		c[i] = a[i] + b[i];
	}

	t_stop = _itoll(TSCH, TSCL);
	t_cn = (t_stop - t_start) - t_overhead;
	printf("test2:%d,%d\n", t_cn, c[1]);
}

link.cmd:

MEMORY
{
  L2SRAM (RWX)  : org = 0x0800000, len = 0x040000 /* 128KB */
  DDR0:      o = 0x80000000 l = 0x40000000   /* 1GB external DDR Bank 0 */
}

SECTIONS
{
  .kernel: {
    dsplib*<*.o*> (.text:optimized) { SIZE(_kernel_size) }
  } 
  
  .text:            load >> DDR0
  .text:touch:      load >> DDR0

  GROUP (NEAR_DP)
  {
    .neardata
    .rodata 
    .bss
  } load > DDR0
   
  .init_array: load >> DDR0 
  .far:        load >> DDR0
  .fardata:    load >> DDR0
  .neardata    load >> DDR0
  .rodata      load >> DDR0
  .data:       load >> DDR0 
  .switch:     load >> DDR0
  .stack:      load >  DDR0
  .args:       load >  DDR0 align = 0x4, fill = 0 {_argsize = 0x200; }
  .sysmem:     load >  DDR0
  .cinit:      load >  DDR0
  .const:      load >  DDR0 START(const_start) SIZE(const_size)
  .pinit:      load >  DDR0
  .cio:        load >> DDR0
  .csl_vect:   load >  DDR0
}

result:

test1:1731405405,8
test2:1731397407,8

As you see, using cache is a little faster than no cache, but I think that using cache naturally must be more faster.

Please tell me what is wrong?

Thanks again.

Regards, Aither.

Hi, Eric.

First, thanks for your reply, and sorry for my late reply.

I tested as you instructed, but the result is same:

t_start_hi = TSCH;
t_start_lo = TSCL;
t_start = _itoll(t_start_hi, t_start_lo);

for (i = 0; i < TEST_BUFF_SZ; i++)
{
c[i] = a[i] + b[i];
}

t_stop_hi = TSCH;
t_stop_lo = TSCL;
t_stop = _itoll(t_stop_hi, t_stop_lo);
t_cn = (t_stop - t_start) - t_overhead;
AUDIO_log("test1:%d,%X,%X~%X,%X\n", t_cn, t_start_hi, t_start_lo, t_stop_hi, t_stop_lo);

test1:1732320338,5,C4CC9980~5,2C0DB5D6

test2:1732253510,6,3297C265~6,99D7D9AF

I could not verify _itoll(), however the difference is very small.

Please tell me to solve this problem.

Thanks again.

Regards.

Aither.