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Setting VBPE clock freq to a low value while ARM processor runs at Max clock(216MHz).

Snehal Parmar
Intellectual 485 points

Hi,

I have an LCD interfaced to a DM355 based board. LCD supports max of 10Mhz frequency.

I have configured DM355 PLL1 to max-432Mhz. I need it to run processor at max frequency.

Now if I choose SYSCLK3 as the VPBE clock then the minimum clock that can be generated is 13.5Mhz(set PLLDIV3 to31).

 

Is there a way/trick to get VBPE frequency to lower than 10Mhz without using an external clock source ?

 

Thanks,

Snehal

 

 

  • 0
    TI__Intellectual 1265 points

    Snehal,

    Yes, you can alter/reduce the the pixel clock with the DCLKPTNx registers.  Note that you will also have to specify the pattern width you want, in the DCLKCTL.DCKPW register bits.

    Example:  DCLKCTL.DCKPW = 0x1, DCLKPTN0 = 0x1 should give you a pattern width of 2 (DCKPW+1) and a pattern of binary '01'.  With DCKEC = 0, this should give you an effective additional divide by 2.  There are many possibilities/divisors you can get from this.

    For more info on this, see 4.5.4.4 of SPRUF72C.

    http://focus.ti.com/lit/ug/spruf72c/spruf72c.pdf

    -Ian

  • 0 in reply to IanB
    Intellectual 485 points

    Hi Ian,

    Thanks for the reply. I am able to generate clock using DCLKCTL and DCLKPTN0 registers.

    But now the video gets garbled after setting the clock through these registers. I doubt that hsync and vsync signals are not getting generated properly.

    Will post my findings.

    Thanks,

    Snehal

     

  • 0 in reply to Snehal Parmar
    Intellectual 485 points

    Thanks Ian for the useful suggestions.

    The issue got solved. The issue was with VENC parameters and OSDCLK0. Once the clock is generated using DCLKCTL registers, then after

    it is needed to adjust venc settings such as hint, hvalid, hstart etc.

    With SYSCLK3 I was able to get good image on LCD. After using clock generated using DCLKCTL register I needed to adjust VENC parameters such that they are the same as they were with SYSCLK3 Effectively(not the exact same values). Also set OSDCLK0 and OSDCLK1 properly.

     

    Thanks,

    Snehal

     


  • 0 in reply to Snehal Parmar
    TI__Intellectual 1265 points

    Glad they helped.  Just to publicize all of the suggestions, below is a basic recipe for halving DCLK (i.e. modifications from original settings)

    DCLKCTL = 0x0801;
    DCLKPTN0 = 0x1; // set clock pattern to obtain half of base clock

    // double VPBE_VENC_HSTART, may have to tweak this some afterward
    // double VPBE_VENC_HVALID 
    // double VPBE_VENC_HINT 

    VENC_OSDCLK0=1;  
    VENC_OSDCLK1=1;  // also set OSD clock divider to match

    -Ian

  • 0 in reply to IanB
    Intellectual 960 points

    i tried basically the same method on DM368 for a 320x240 LCD, ie, using DCLKCTL/DCLKPTN0 and OSDCLK0/OSDCLK1 to mask 27MHz VENC clock to generate 6.75MHz DCLK for LCD. The DCLK generated is measured correct, so are HSYNC, VSYNC, HINT, and HVALID correctly multiplied by 4.

    I believe the OSD side of registers equpvalent of HINT and HVALID need to be modified too.

    However, I am not getting correct result. The OSD picture looks like horizontally compressed. Now I believe the actual RGB data pulse is still based on 27MHz VENC clock, not DCLK. Therefore the data lines are not synchronized with DCLK. Because data pulse is 4 times smaller, 4 pixels (in horizontal direction) is only samples once by the LCD following 6.75MHz DCLK.

    My question is does RGB data pulse following VENC or DCLK? Anyone can confirm this? In my test, it clearly follows VENC which makes this impossible to work.