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RTOS/AM5746: how to realize USB2.0 on USB1

matusan
Guru 10235 points

Part Number: AM5746

Tool/software: TI-RTOS

Hello, TI Experts,

 

Our customer sent us questions about USB with PROCESSOR-SDK-RTOS-AM57X.

They would like to use USB1 as USB2.0 on TMDSIDK574.

 

Question:

Could you tell us how to realize USB2.0 on USB1 of AM5746.

   - Are there any related sample code?

   - How to modify the sample code?

 

Best regards,

  • 0
    TI__Guru* 95265 points
    Hi,

    The USB1 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0) PHY and HS/FS (USB2.0) PHY, so it also supports USB 2.0 device.

    Can you confirm that you want to limit the USB1 port to USB 2.0 only? I thought you need to disable USBOTGSS_CLK and USBOTGSS_USBPHY.

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points
    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.

    Our customer said "they want to use the USB1 port to USB 2.0 only".
    So, I'd like to answer to the customer like below which you said.
    "You need to disable USBOTGSS_CLK and USBOTGSS_USBPHY."

    If you have additional comment or notice , please tell us.

    Best regards,
  • 0 in reply to matusan
    TI__Guru* 95265 points
    Hi,

    We don't have this code but you may try below:

    1. There is a code inside usbClockCfg(), comment this out:

    if (portNumber==0){
    USBOTGSS_CLKCONFIG_Vayu_DPLL_USB_OTG_SS(); /* USB3 PLL - without PLL, Port never reaches U0 */
    USBOTGSS_USBPHY_PowerSequence_VAYU(portNumber);

    }

    2. There might be another 2 bits that need to turn off (if they happen to be ON by default)

    /* CLK_CMD presumebly is (3 << 14) to enable both RX & TX */
    reg = HW_RD_REG32(CTRL_CORE_PHY_POWER_USB);
    reg |= (3<<14);
    HW_WR_REG32(CTRL_CORE_PHY_POWER_USB, reg);

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points
    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.

    We found related descripition in
    C:\ti\pdk_am57xx_1_0_11\packages\ti\drv\usb\soc\am574x\usb_wrapper.c

    Our understanding is like below:

    1:comment out below two to disable USBOTGSS_CLK and USBOTGSS_USBPHY which you said.
    // USBOTGSS_CLKCONFIG_Vayu_DPLL_USB_OTG_SS(); /* USB3 PLL - without PLL, Port never reaches U0 */
    // USBOTGSS_USBPHY_PowerSequence_VAYU(portNumber);

    2:comment out below two
    // reg |= (3<<14);
    // HW_WR_REG32(CTRL_CORE_PHY_POWER_USB, reg);

    Because you thought it is not necessary to set below two bit in "Table 18-156. CTRL_CORE_PHY_POWER_USB" of TRM.
    - Bit[14] - 0x1: Powers-up the USB3_PHY_RX
    - Bit[15] - 0x1: Powers-up the USB3_PHY_TX

    Is this understanding correct?

    Best regards,
  • 0 in reply to matusan
    TI__Guru* 95265 points
    Hi,

    For 1, correct.
    For 2, correct. Just make sure BIT 14 and 15 are 0 after reset.

    Regards, Eric
  • 0 in reply to lding
    Guru 10235 points
    Hi,

    Thank you very much for your kindness.
    I really appreciate your help.
    I will send the answer to the customer.

    Best regards,