AM5728: EVM DDR3 layout conflicts to constraint setting.

Layla Chen

Part Number: AM5728

There are some DDR3 spacing on board which is not follow spacing 10mil in constraint setting.

For example, constraint rule is 10 mil (diagram #1) but actually it's between 5mil and 10 mil on board (diagram #2, #3).

diagram #1

diagram #2

diagram #3

over 6 years ago

0 Biser Gatchev-XID over 6 years ago

TI__Guru**** 393215 points

Hi,

See Note 9 below Table 8-12, and Note 5 below Table 8-13 in the AM572x Datasheet SR2.0 Rev. E.

0 Layla Chen over 6 years ago in reply to Biser Gatchev-XID

Prodigy 50 points

Thank you, sir.

Is there any suggested simulation method and spec for DDR3?

0 JJD over 6 years ago in reply to Layla Chen

TI__Guru* 85820 points

Layla, we don't have a suggested simulation method. Several customers use Hyperlinx with our IBIS models to perform signal integrity simulations.

Regards,
James

0 Layla Chen over 6 years ago in reply to JJD

Prodigy 50 points

Hi sir,

We are doing DDR3 simulation by Hyperlinx. We have some questions as below.

1. What suggestion do you have for ODT setting for controller and DRAM?

2.What Model could be select to the corresponding model selector?

0 JJD over 6 years ago in reply to Layla Chen

TI__Guru* 85820 points

Hi Layla, please refer to this wiki: processors.wiki.ti.com/.../How_to_use_the_AM335x_IBIS_Models

It refers to a different processor, but most of the information applies to the AM572x.

Regards,
James

Processors

Processors forum

AM5728: EVM DDR3 layout conflicts to constraint setting.