OMAPL138B-EP: Double Writing Strobes (EMA_Wen) while using 16-bit Normal Mode EMIF.

Hi,

Could you share the timings captured with the logic analyzer?

Best Regards,
Yordan

CS= -------_____________________--------
EMA_WEn= --------__________--________-------------

Sorry, I cant really send you the snapshot, but this is the least i could share it with you.
Need urgent reply.

Hi Awais,

What device are you communicating with? It sounds like it is asynchronous. Can you confirm?

What data type are you writing to the EMIF16? Can you paste the code here?

Perhaps if you are writing 32-bits, the EMIF will perform a two cycle write with each 16-bit part of the 32-bits without raising CS.

If so, try writing just 16-bits by defining the pointer to EMIF space as Uint16 or uint16_t.

Does OEn have two low pulses during a read from EMIF to the same data type?

See this similar post about two write pulses...

https://e2e.ti.com/support/processors/f/791/t/144454

Do you have access to the DQM signals on your logic analyzer?

 <-- Table 20-20 EMIF16 Asynch Write Operation in Normal Mode from SPRUH77C

Regards,
Mark

OMAPL138 EMIF CS4 is connected with 8-bit ASRAM (This RAM is realized in Spartan 6 FPGA). Whenever, we do any transaction (Read/Write) with ASRAM to access 8-bits only in 1 clock cycle, EMA_OEn and EMA_WEn go low FOUR times during single transaction. Therefore, we are unable to read or write 8-bits. This shows that we can read or write 32-bits only during single transaction. However, we want to access only 8-bits in one transaction.

Similarly, we have configured EMIF with 16-bits then EMA_OEn and EMA_WEn go low TWO times during single transaction.

KINDLY, help us regarding configuration of EMIF for 8-bit transaction and its related settings using ARM core.

Refer to www.ti.com/lit/ug/sprufl6f/sprufl6f.pdf.
page # 31 of 84 figure 10. EMA_OE goes low only once. However, we are not getting this kind of response instead in our case EMA_OE goes low more than once in one transaction.