DM365 capture interlaced video from CCD without embedded sync

I also want to use VPFE with out sync pulses and my in coming data is totally in non standard format, 

Can you guide me how I can use VPFE to capture data and store it onto memory wihout any processing ??

Thank you very much.

I use it only for capture real picture from camera with the vertical and horizontal syncs - using standard application stack based on: Encode demo (dvsdk_demos_2_10_00_17) -> DMAI (dmai_1_21_00_10) -> VPFE driver. And I modify standard TVP7002.c driver to switch video multiplexer to work with CCD-DATA (on EVMDM365 board). I did not find the standard solution to do this.

In this way the incoming data are not processed (if You do not enable features such Scaling).

Also there should be possible to receive limited number of data without being interrupted by sync signals (see vpfe document for limitation of line length. e.g. input data formatter limit for 4736 pixels and probably other limits). In this case You probably will need to edit standard DMAI and davinci_vpfe.c (linux driver) for using for such strange usage (e.g. frame size 1024 x 1 to capture single frame with single line).

Maybe simplier way for You will be to adopt application demo for Leopard Imaging sensor with disabled data processing (capture_prev_rsz_onthe_fly_bayer). It use the driver mt9p031.c.

hmm..thanks a lot for ur reply...

I have data in quite non standard format..see figure below...

I just want to know ...

1- Is it possible to capture such data using vpfe , if PCLK=10-15 MHz??

2-I have only 8 bit data and PCLK then what is the feasibility of using VPFE ?

3- IF yes then exactly which files do i need to modify ?? My IC uses SPI communication.... 

If i can use then I will take complete data into DDR than using ARM / EDMA i will sort pixel data and regenerate whole image and than insert it into IPIPE ..wt so u say ????

1. I think, that it will be problem to capture such continuous signal with VPFE. If there will be sync pulses (Vert/Horiz), it will be possible. Frequency of PCLK can be up to 120MHz, so 10-15 should be ok.

2. 8 bit data can be captured like Y channel. You can ignore Cr/Cb channel.

3. [:S] this is not very easy, because it is quite complex engine with many configuration registers. Focus to study the document of VPFE and linux sources:

  /drivers/media/video/davinci

  /drivers/char/dm365..., davinci_...

Juraj's assesment is correct.  This is a video interface which means eventually there will need to be some hsync/vsync signals to mark the beginning of a new line or frame of video.  These syncs may be embedded with the data as in BT.656 or BT.1120 standards or discrete via dedicated hardware pins.  The hardware has a limitation on the maximum size of frame (line length  and lines per frame), hence you can certainly define hardware registers to have as few syncs as possible and to have them be as short as possible, but they will need to happen when you reach the max line length or lines per frame.  This is just the nature of a video port, it is not truly continous, syncs are part of the equation.

what type of device is feeding the DM365?  FPGA or another video part (which should also contain syncs)...if it is just a matter of tranferring the data and you have some type of control over the source device, than at the 10-15 rate you require, you can certainly design a proprietary protocol to accomplish this (pass relevant data during valid video portion and avoid passing data during syncs...).