RTOS/AM5746: MMU setting policy of sample projects in PROCESSOR-SDK-RTOS-AM57X

Matusan,

Is the question related to bare-metal or TI RTOS examples ?  The MMU settings for both the setups is done differently.

For bare-metal code:

The MMU settings for bare-metal A15 applications is done using the CSL Init library (ti.csl.init.aa15fg). The source code and setting of the MMU is part of the A15 core initialization which you can find in the source files mmu_a15.c and mmu_a15_gcc.asm in folder pdk_am57xx_x_x_xx\packages\ti\csl\arch\a15\v1.  The MMU settings typically need to be done when the device is in SVC (supervisor state). This initialization of the core is designed to run before executing application main. the device reset vector will start execution of the intiialization code and then branch to main to allow execution.

For TI RTOS application:

The code that performs MMU configuration is in the MMU.c file for the appropriate ARM core in question. For example for A15, refer to the MMU source file here:

bios_6_73_01_01\packages\ti\sysbios\family\arm\a15

User can update/override the MMU settings applied as part of BIOS configuration using .cfg file 

Example:

/* ================ Cache and MMU configuration ================ */

var Cache1 = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');

/* Enable cache */
Cache1.enableCache = true;

/* Enable the MMU (Required for L1 data caching) */
Mmu.enableMMU = true;

var attrs = new Mmu.DescriptorAttrs();
Mmu.initDescAttrsMeta(attrs);
attrs.type = Mmu.DescriptorType_BLOCK;
attrs.noExecute = true;
attrs.accPerm = 0; // R/W at PL1
attrs.attrIndx = 7; // Use MAIR0 Byte7
Mmu.setMAIRMeta(7, 0x04);

Mmu.setSecondLevelDescMeta(0x43200000, 0x43200000, attrs);
Mmu.setSecondLevelDescMeta(0xA0000000, 0xA0000000, attrs); /* APP_UNCACHED_DATA_BLK3_MEM */

to confirm that the MMU setting is applied, in debug view you can enable the ROV view and look at the page tables setup and the attributes setup. CCS REgister view also alllows users to read the core supervisor registers to read back the MMU setup and hte attributes setup for each region but doesn`t have a way to interpret them.  Code composer studio may not have the best of features to debug MMU related issues. You look at other trace tools like LAuterbach/Trace32 to optimize the MMU settings.

We also recommend the Cortex A Programmers guide to understand more about setting MMU And cache :

https://www.macs.hw.ac.uk/~hwloidl/Courses/F28HS/Docu/DEN0013D_cortex_a_series_PG.pdf 

Following tools are available for application developers to check on MMU status:

ARM Advanced Tools:

Under Tools-> ARM Advanced tools , you can check if MMU is enabled or disabled but translation information is not available. You can check out the screen shot below:

CCS Register View to check ARM CP15 Registers:

ROV Classic tool for RTOS:

For RTOS developers the Level 1 and Level 2 setup can be read back using the ROV Classic View as shown bellow