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OMAP-L138: Asynchronous EMIF Interface Wait

Matt Foth
Prodigy 20 points
Part Number: OMAP-L138


I'm working with an FPGA design that interfaces to the EMIF asynchronous interface and utilizes wait states based on addressing. Due to the asynchronous nature, it is challenging to determine when to assert the EM_WAIT signal quickly enough. I can meet the setup time required by No. 28 of Table 6-23 of the datasheet of 4E+3 nanoseconds of setup time.

What I'm concerned about is that the FPGA design may assert or de-assert the EM_WAIT just previous to the setup time (depending on how quickly it can determine by the address if a wait state is necessary) and the duration of those pulses can be less than 2E, the minimum pulse duration of EM_WAIT from No. 2 of Table 6-23 of the datasheet.

Is it possible that these short pulses of EM_WAIT could cause metastability issues on the DSP's EMIF interface or will it be okay as long as the EM_WAIT is stable by the required setup time?

  • 0
    TI__Mastermind 30210 points
    Hi Matt,

    I think as long as setup time is satisfied then WAIT can be unknown before the setup time requirement as depicted by the gray waveform in Figure 6-16 and Figure 6-17 in the datasheet.

    This would play into the requirement described in TRM section 18.2.5.7 Extended Wait Mode and the EMA_WAIT Pin:
    Finally, a restriction is placed on the strobe period timing parameters when operating in Extended Wait mode. Specifically, the sum of the W_SETUP and W_STROBE fields must be greater than 4, and the sum of the R_SETUP and R_STROBE fields must be greater than 4 for the EMIFA to recognize the EMA_WAIT pin has been asserted.

    I will follow up with the designer to verify and ensure there would be no instabilities caused by a WAIT pulse shorter than 2E. Should have an answer for you by tomorrow or Monday.

    Regards,
    Mark
  • 0 in reply to Mark M
    TI__Mastermind 30210 points
    Hi Matt,

    Just wanted to let you know that the designer is still looking at this matter. Lets give him a couple more days. I'll check in here by Wednesday.

    Regards,
    Mark
  • 0 in reply to Mark M
    Prodigy 20 points
    Thank you, Mark. I look forward to the response from the designer

    Matt
  • 0 in reply to Matt Foth
    TI__Mastermind 30210 points
    Hi Matt,

    Here's what I found out.

    The WAIT signal has a synchronizer inside. For an assertion to make it through the synchronizer, it has to be asserted at least for 2 clock cycles. That is what the data sheet lists (2E).

    So if your WAIT pulse is less than 2E, it will not affect the EMIF operation.
    It should be okay as long as the EM_WAIT is stable by the required setup time and satisfies the 2E pulse requirement if asserted.

    Regards,
    Mark