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TMS320C6678: Does C6678 support single rank but twin-die SDRAM?

Snaku Lee26
Intellectual 310 points
Part Number: TMS320C6678

Hi,

The DDR3, 'MT41K512M16HA', which I used will be EOL, so my vendor provide me a same size and pin compatible device, 'MT41K512M16VRN', but it is a twin-die SDRAM.

I read the "KeyStone I DDR3 Initialization" (SPRABL2E) document, the chapter 4 describes the guideline for dual rank twin-die SDRAM, but it is for dual rank device right?

I think my real question is that what's different between 'single rank twin-die' and 'single rank monolithic die' if their total density is the same? Should I take any other action when I initialize the DDR3 memory for single rank twin-die SDRAM?

Regards,

Snaku

  • 0
    TI__Mastermind 46460 points

    Snaku,

    Single rank monolithic means that each SDRAM has one die in it.  This means each SDRAM only has one load on each data, address and control pin.

    There is no such thing as a single-rank twin-die device.  I twin-die device has two dies in a single package resulting in 2 loads on each address and data pin and requires two sets of control pins.  This is a dual-rank implementation.  Therefore, this is significantly different from an electrical perspective and it requires several software modifications.

    The KeyStone I DDR3 Initialization Application Report (SPRABL2E) does discuss support for twin die / dual rank topologies in Section 4.  However, based on customer implementation difficulty and the availability of large, cost-effective, monolithic SDRAMs, we are not promoting use of twin-die devices.  (There are multiple E2E threads on this topic.)  8Gb monolithic devices are readily available and cost effective so we recommend that customers use them to implement 8GB memory arrays.

    We are aware that some DDR3 part numbers are being obsoleted but there are alternatives that can be dropped in without PCB modification or software modification.  Normally, this is a higher speed grade.  Also note that DDR3 part numbers have been obsoleted by most manufacturers and replaced by DDR3L devices.  Per JEDEC, all DDR3L devices can be operated at 1.5V.  Please discuss this with your SDRAM supplier.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 310 points

    Hi Tom,

    This is the functional block of the twin-die device, there is only one set control pins, so it is a single rank device, right?

    Thanks for your quick reply.

    Snaku

  • 0 in reply to Snaku Lee26
    TI__Mastermind 46460 points

    Snaku,

    Understood.  I am not familiar with twin-die SDRAMs with that arrangement.  These have single loads on the data pins but two loads on all address, command, control and clock.  This is still a concern from the electrical load perspective although it should level same as a single rank topology using single die devices.  What is the SDRAM arrangement in your topology - i.e. how many SDRAMs of what density?

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Snaku,

    Can you provide the requested information?

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 310 points

    Hi Tom,

    Sorry for my late reply.

    My SDRAMs topology is typical fly-by, four SDRAM device, each density is 512 Mega x 16 , so total size is 4GB DDR3.

    Thank you,

    Snaku

  • 0 in reply to Snaku Lee26
    TI__Mastermind 46460 points

    Snaku,

    As I said before, I am not familiar with this type of twin-die SDRAM.  However, since the memory rank of SDRAM will look like 8 individual SDRAM chips on a single chip select, it should level and operate at the rated speeds.  This topology will have 2 Address, Command, Control and Clock loads per SDRAM pin and only a single load on each data pin.  It should look electrically same as if you implemented a single rank of 8 SDRAMs each in an x8 configuration.  Be sure to follow the guidance in the DDR3 interface commissioning wiki:

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Skaku,

    I just looked back at the original question.  You were asking whether the twin-die device could be dropped into an existing board that is already in production.  I believe this should drop in and operate without software change.  However, the electrical loading will be different with the twin-die SDRAM.  Therefore, there will be a difference in the signal integrity.  If your existing design followed all of our guidelines, I believe it will work robustly at the rated speed using these twin-die devices.  However, if your design has reduced margin, then the increase in the electrical loads may cause a problem.  You will need to get samples of these alternate devices and then re-qualify your design.  Alternately, you might want to find a different SDRAM in the same x16 configuration that you originally qualified.

    Tom

  • 0 in reply to Tom Johnson 16214
    Intellectual 310 points

    Hi Tom,

    Thanks for your information, I will do some test with the twin-die SDRAM.

    Regards,

    Snaku