Part Number: AM5748
Our customer checked the result of full leveling and then have a question about the result of write leveling. The result of write leveling in the EMIF_PHY_STATUS_x registers is as follows:
EMIF1_EMIF_PHY_STATUS_17.PHY_REG_WRLVL_DQ_RATIO0 = 98
EMIF1_EMIF_PHY_STATUS_18.PHY_REG_WRLVL_DQ_RATIO2 = 95
EMIF1_EMIF_PHY_STATUS_19.PHY_REG_WRLVL_DQ_RATIO4 = 109
EMIF1_EMIF_PHY_STATUS_20.PHY_REG_WRLVL_DQ_RATIO6 = 107
EMIF1_EMIF_PHY_STATUS_21.PHY_REG_WRLVL_DQ_RATIO8 = 120
EMIF1_EMIF_PHY_STATUS_22.PHY_REG_WRLVL_DQS_RATIO0 = 66
EMIF1_EMIF_PHY_STATUS_23.PHY_REG_WRLVL_DQS_RATIO2 = 63
EMIF1_EMIF_PHY_STATUS_24.PHY_REG_WRLVL_DQS_RATIO4 = 77
EMIF1_EMIF_PHY_STATUS_25.PHY_REG_WRLVL_DQS_RATIO6 = 75
EMIF1_EMIF_PHY_STATUS_26.PHY_REG_WRLVL_DQS_RATIO8 = 88
WRLVL_DQS_RATIOx for DQS, WRLVL_DQ_RATIOx for the DQ, each of them will indicate a delay value from the rising edge of CK. The goal of write leveling is to locate the delay between the rising edge of the write DQS signal and the rising edge of the SDRAM memory clock (CK), but does not mention the DQ signal.
1) Does the write leveling locate the delay between the rising edge of the DQ signal and the rising edge of CK?
The difference between WRLVL_DQS_RATIOx and WRLVL_DQ_RATIOx in each of data macro indicates the same value for all data macros.
WRLVL_DQ_RATIO0 - WRLVL_DQS_RATIO0 = 98 - 66 = 32
WRLVL_DQ_RATIO2 - WRLVL_DQS_RATIO2 = 95 - 63 = 32
WRLVL_DQ_RATIO4 - WRLVL_DQS_RATIO4 = 109 - 77 = 32
WRLVL_DQ_RATIO6 - WRLVL_DQS_RATIO6 = 107 - 75 = 32
WRLVL_DQ_RATIO8 - WRLVL_DQS_RATIO8 = 120 - 88 = 32
Each of delay values is the fraction of a clock cycle in units of 256ths. So that the difference between WRLVL_DQS_RATIOx and WRLVL_DQ_RATIOx is 32 indicates that the phase difference between DQS signal and DQ signal is 45 degrees (32/256 = 1/8).
2) Is WRLVL_DQ_RATIOx calculated based on WRLVL_DQS_RATIOx?
3) In this case, was the value of WRLVL_DQS_RATIOx plus 32 (45 degree phase difference) used for?
Our customer is testing whether the HW leveling is better than SW leveling because the HW leveling was not supported on products older than AM574x. The value of WRLVL_DQ_RATIOx is very different between the result of HW leveling and the result of SW leveling.
Best regards,
Daisuke
