RTOS/TDA3: TDA3 "EMIF1 ECC CONFIGURATION" problem

Denny Zhuang

Intellectual 460 points

Part Number: TDA3

Tool/software: TI-RTOS

Hi,

I am using CCSv8 to debug our custom board.

The EMIF1 connected to 1GB ddr3 with 256MB ecc.

I connected the IPU1_C0 without ecc_enable,and the memory range of EMIF1 looked good.

After run the script ecc_enable,the memory range of emif1 looked strange.

Is it right?

Here is my gel.

TDA3xx_ddr_config.gel

over 6 years ago

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi Denny,

Did you initialize the ECC values by doing a memfill after enabling ECC?

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

You can refer to www.ti.com/.../sprac42b.pdf on how to enable ECC

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi,
Which etc values?

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi,
I've already followed the steps to enable the emif ecc. The problems is still there.

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi,

I do not understand what you mean by "etc values".
After enabling ECC you need to write to DDR before doing any accesses otherwise you will get false errors.
Can you read ECC registers from 0x4C000110 to 0x4C000140 after enabling ECC and share the dump.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi,
Sorry,it's "ecc values",not "etc values".
After ran the ecc-enable script, I could't load any program to m4.
What do you mean about writing to DDR? Doesn't loading program to m4 write to DDR?

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi,

I am referring to step 6 of section 2.2.
Can you share the register values as asked previously.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi,

I will give the information you need on 2/11.

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi,

In that case I am closing this thread till then.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi,

Before running the script " TDA3xx_EMIF1_ECC_Configuration ", the ECC registers from 0x4C000110 to 0x4C000140 are

After running the script " TDA3xx_EMIF1_ECC_Configuration ", the ECC registers from 0x4C000110 to 0x4C000140 are

BR,Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

You are getting a lot of ECC errors, maybe memory is becoming in accessible due to this.
See API SBLUtilsEmifECCConfigure in PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\boot\sbl_auto\sbl_utils\src\sbl_utils_common.c on how to enable ECC and prefill the memory.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

8407.TDA3xx_ddr_config.gelHi,

Please check my gel file "TDA3xx_ddr_config".

BR,Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi,

Gel file alone is not sufficient. You need to follow the sequence given in SBL.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi Rishabh Garg,

I will try to follow the sequence in SBL you have mentioned to modify the GEL.

By the way, isn't there any existing source that can use on CCS to test the function of EMIF ECC?

I just want to test the DDR3 using for ECC if the function is well or not.

BR,Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

Enabling ECC involves two parts:
1. ECC configuration
2. Prefilling DDR using EDMA
Gels can only do the first part. You need to run an executable to do the second part.
In case you have SBL you can use the same to enable EMIF ECC for desired memory range.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi Rishabh Garg,

I can't understand the second steps "2. Prefilling DDR using EDMA".

Do you mean that we can not load program to ipu1_0 after running the script "TDA3xx_EMIF1_ECC_Configuration"?

There is a test app in PDK called "csl_ecc_test_app".

Can use this app to check if the function of EMIF ECC is correct or not?

BR,Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

Yes you need to prime the DDR before accessing it to avoid ECC errors.
You can also use ECC app csl_ecc_test_app to check EMIF ECC.
This application uses CPU to prime DDR which is slower as compared to EDMA.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi Rishabh Garg,

Do I need to do any changes in the original GEL files? I mean the original GEL files in CCSv8 did not enable ECC.

Do I need to enable ECC in the GEL before connecting to the ipu1_0 and then running the csl_ecc_test_app?

BR,Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

Please see processors.wiki.ti.com/.../PDK_TDA_CSL_User_Guide

Regards,
Rishabh

0 Rishabh Garg over 6 years ago in reply to Rishabh Garg

TI__Guru 55685 points

Hi Denny,

Are you able to get this working?

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi Rishabh Garg,

I ran the csl_ecc_test_app on CCS, but it could execute well.

The teraterm message hanged like this.

I checked the c code in the C:\PROCESSOR_SDK_VISION_03_06_00_00\ti_components\drivers\pdk_01_10_02_07\packages\ti\csl\example\ecc\ecc_test_app\ecc_emif.c

and found this

Therefore, I modified the GEL in the CCS .

I ran the test again. This time I ran the script EMIF1_ECC_Configuration() first to make sure the register CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT set well.

Everything went well after I have done these changes.

By the way, I have some questions about setting EMIF_ECC_START_ADDR & EMIF_ECC_END_ADDR in csl_ecc_test_app.

The default setting is 0x90000000~0X9001FFFF.

Can't I set the ECC range for whole 1GB ddr3 (0x80000000~0xBFFFFFFF)?

I done this change and the app hanged again.

BR,Denny

0 Denny Zhuang over 6 years ago in reply to Denny Zhuang

Intellectual 460 points

Replace the first image.

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

The example code is executing from DDR. Hence you are running into issue of initialization.
You can update the linker command file to use OCMC and then update the DDR start address and end address to whole DDR.
Also as the app is doing CPU copy it will take a long time to prefill whole DDR memory.
Maybe you are seeing hang on that particular line of code.

Regards,
Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi Rishabh Garg,

To avoid the same issue happened in SBL, how can I decide the ECC range?

At SBL step, SBL will load the app code to the ddr3.

The ECC range should not contain the range where app code live,right?

BR,Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

SBL will setup the ECC and prefill memory so you should not face any problem with SBL.

In other words ECC range can/cannot contain the range where app code is running, depending on the use case.

Regards,

Rishabh

0 Denny Zhuang over 6 years ago in reply to Rishabh Garg

Intellectual 460 points

Hi Rishabh,

Till now, I still confuse about "prefill memory".
Is there any source for me to study?
The information you give for me said that sometimes the ECC range may contain the area where app code running. It all depends on the usecase we choose.
Is there any guideline or standard for me to follow about this situation?

Regards,

Denny

0 Rishabh Garg over 6 years ago in reply to Denny Zhuang

TI__Guru 55685 points

Hi Denny,

The DDR and ECC parity bits are uninitialized when the SoC is first powered on.
DDR initialization is needed so that the ECC checksum memory gets initialized properly.
First step for software is to first initialize the whole memory after enabling the ECC. This step is called prefilling memory.
This step would ensure that the parity bits are correctly set before the code access to ECC enabled regions.
This step would ensure that ECC error scenarios are not generated for uninitialized parity data.
This step can be done by either the CPU memset or the EDMA transfer to the memory region.
The details are captured here:www.ti.com/.../sprac42b.pdf
If you want further documentation you can refer to EMIF chapter in TRM: www.ti.com/.../spruie7c.pdf
We have CSL example for EMIF ECC.
EMIF ECC is also enabled in the SBL.

Regards,
Rishabh

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RTOS/TDA3: TDA3 "EMIF1 ECC CONFIGURATION" problem