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Help with Flashing Micron NAND & DM365

Kevin Claycomb
Intellectual 420 points
Other Parts Discussed in Thread: CCSTUDIO

I am trying to use a Micron MT29F16G08DAA 2GB NAND Flash with the DM365 EVM instead of the FAA part.  This part has 4K page size, 218 byte spare, and 256K block size vs the 2K page, 64 spare and 128K block.  By my reading of the ARM subsytem users guide this should be supported.   I have tried both using JTAG with CCS and the DM365-Install instructions that come with the PSP as well as Constantine's SD boot/flash utility.  Both methods report flash success and apperar to work just fine, but when I reboot the board to bring up u-boot I get nothing out of the serial port.  I have a correctly flashed FAA part so I can verify that the board is working. 

I have also contacted my TI rep and he verified on his end with the same part that it doesn't boot, but believes that it should have worked??  After doing some digging it appears that the DAA part reports the same device ID 0xD3 as the FAA part even though they are layed out a little different.  It should still be able to read the memory organization area and determine the correct parameters, right?  It looks like RBL should support this, but the NANDWriter /Eraser program may need to be updated to write/erase the everything correctly?  

Has anyone else had any experience with the DAA micron parts and the DM365? Thoughts or things to try?  I am going to be looking at the NANDWriter source that came with the PSP in flash_utils to see if I can pin down what is going on.

 

 

  • TI__Mastermind 37340 points

    Your assesment sounds correct; according to our hardware experts, MT29F16G08DAA NAND part should work with DM365.  However, the NANDwritter utilities provided do not support all the possible NAND devices DM365 can support; it is likely updated every now and then to support the NAND device included on our EVMs; this means that whenever a different NAND device is chosen, you may need to update NANDWritter, U-boot, and perhaps Linux Kernel.

  • in reply to Juan Gonzales
    Intellectual 420 points

    I have the NANDEraser code in CCS 3.3, but I admit that this is once of my first ventures into CCS.  I am fighting a linking error, hopefully someone can point me to the right library/file to add in for this.  I have loaded the .pjt file provided in the PSP for the NANDEraser into CCS.  I am getting these errors

    -------------------

    [Linking...] "C:\CCStudio_v3.3\tms470\cgtools\bin\cl470" -@"Debug.lkf"
    <Linking>

    undefined                        first referenced
     symbol                              in file
    ---------                        ----------------
    _EXTERNAL_RAM_END                C:\Documents and Settings\ClaycKe\Desktop\TI Davinci\NAND_Project\flash_utils\DM36x\CCS\NANDEraser\Debug\util.obj
    _EXTERNAL_RAM_START              C:\Documents and Settings\ClaycKe\Desktop\TI Davinci\NAND_Project\flash_utils\DM36x\CCS\NANDEraser\Debug\util.obj
    >>   error: symbol referencing errors - './Debug/NANDEraser_DM36x.out' not built

    >> Compilation failure

    Build Complete,
      2 Errors, 4 Warnings, 0 Remarks.

    --------------------

    Is there a project configuration that I need to setup that wouldn't have been brought in with the .pjt file???  

    Thanks for the help,

    Kevin

  • in reply to Kevin Claycomb
    Intellectual 420 points

    My code generation tools in CCS were out of date.  Solved it by following the wiki page....

    http://wiki.davincidsp.com/index.php/How_to_update_CCS_ARM_cgtools_to_build_the_DM365_ubl_in_CCS_3.3

     

  • in reply to Kevin Claycomb
    Intellectual 420 points

    OK, after spending some time stepping through the NANDWriter/Eraser program it appears to be functioning correctly.  It is definitely correctly extracting the NAND device information including page size, spare bytes, etc from the Parameter Page Data structure in the NAND chip.  I can see via the watch window that these numbers are coming in fine and being used to calculate the number of blocks required for writing UBL, etc...   After looking at UBL, I believe if RBL was getting to UBL at all I would see UBL output some Diag info on the serial port??  This leads me to believe that RBL may not be correctly handling this NAND chip and thus UBL never runs, but I would be very happy to find out I am wrong.  

    Also, there are some vague references to using a different UBL_MAGIC number for big block NAND devices in the ARM subsystem guide page 176.  It is not clear whether or not RBL will correctly use the information in the NAND parameter page or if it will just use the table information?  Is there documentation on the inner workings of RBL anywhere outside of this document?  Have there been any updates to RBL in the V1.2 silicon?  I have a V1.1 TMX part on both of my DM365evms. 

    I seem to be stuck here, anybody have any ideas w.r.t. things to try?

     

     

     

  • in reply to Juan Gonzales
    Prodigy 70 points

    I have a new nand flash chip, MT29F16G08DAA, and  I try to flash the ubl and uboot into the chip,but  I failed ,Juan, what's wrong with this?thanks!

    Target:Writing header and image data to Block 0x0000000B, Page 0x00000000
    Target:Erasing block 0x0000000C through 0x0000000C.
    Target:Writing header and image data to Block 0x0000000C, Page 0x00000000
    Target:Erasing block 0x0000000D through 0x0000000D.
    Target:Writing header and image data to Block 0x0000000D, Page 0x00000000
    Target:Erasing block 0x0000000E through 0x0000000E.
    Target:Writing header and image data to Block 0x0000000E, Page 0x00000000
    Target:Erasing block 0x0000000F through 0x0000000F.
    Target:Writing header and image data to Block 0x0000000F, Page 0x00000000
    Target:Erasing block 0x00000010 through 0x00000010.
    Target:Writing header and image data to Block 0x00000010, Page 0x00000000
    Target:Erasing block 0x00000011 through 0x00000011.
    Target:Writing header and image data to Block 0x00000011, Page 0x00000000
    Target:Erasing block 0x00000012 through 0x00000012.
    Target:Writing header and image data to Block 0x00000012, Page 0x00000000
    Target:Erasing block 0x00000013 through 0x00000013.
    Target:Writing header and image data to Block 0x00000013, Page 0x00000000
    Target:Erasing block 0x00000014 through 0x00000014.
    Target:Writing header and image data to Block 0x00000014, Page 0x00000000
    Target:Erasing block 0x00000015 through 0x00000015.
    Target:Writing header and image data to Block 0x00000015, Page 0x00000000
    Target:Erasing block 0x00000016 through 0x00000016.
    Target:Writing header and image data to Block 0x00000016, Page 0x00000000
    Target:Erasing block 0x00000017 through 0x00000017.
    Target:Writing header and image data to Block 0x00000017, Page 0x00000000
    Target:Erasing block 0x00000018 through 0x00000018.
    Target:Writing header and image data to Block 0x00000018, Page 0x00000000
    Target:Protecting the entire NAND flash.
    Target:   DONE
    Sending the Application image
    Waiting for SENDIMG sequence...
    SENDIMG received. Returning ACK and header for image data...
    ACK command sent. Waiting for BEGIN command...
    BEGIN commmand received.
       0% [ ------------------------------------------------------------ ]
    Status Undefined

     100%                                                              
    Waiting for DONE...        Image data sent.
    DONE received.  All bytes of image data received...
    Target:Writing APP to NAND flash
    Target:Unprotecting blocks 0x00000019 through 0x00000032.
    Target:Number of blocks needed for header and data: 0x0x00000001
    Target:Attempting to start in block number 0x0x00000019.
    Target:Erasing block 0x00000019 through 0x00000019.
    Target:Writing header and image data to Block 0x00000019, Page 0x00000000
    Target:Erasing block 0x0000001A through 0x0000001A.
    Target:Writing header and image data to Block 0x0000001A, Page 0x00000000
    Target:Erasing block 0x0000001B through 0x0000001B.
    Target:Writing header and image data to Block 0x0000001B, Page 0x00000000
    Target:Erasing block 0x0000001C through 0x0000001C.
    Target:Writing header and image data to Block 0x0000001C, Page 0x00000000
    Target:Erasing block 0x0000001D through 0x0000001D.
    Target:Writing header and image data to Block 0x0000001D, Page 0x00000000
    Target:Erasing block 0x0000001E through 0x0000001E.
    Target:Writing header and image data to Block 0x0000001E, Page 0x00000000
    Target:Erasing block 0x0000001F through 0x0000001F.
    Target:Writing header and image data to Block 0x0000001F, Page 0x00000000
    Target:Erasing block 0x00000020 through 0x00000020.
    Target:Writing header and image data to Block 0x00000020, Page 0x00000000
    Target:Erasing block 0x00000021 through 0x00000021.
    Target:Writing header and image data to Block 0x00000021, Page 0x00000000
    Target:Erasing block 0x00000022 through 0x00000022.
    Target:Writing header and image data to Block 0x00000022, Page 0x00000000
    Target:Erasing block 0x00000023 through 0x00000023.
    Target:Writing header and image data to Block 0x00000023, Page 0x00000000
    Target:Erasing block 0x00000024 through 0x00000024.
    Target:Writing header and image data to Block 0x00000024, Page 0x00000000
    Target:Erasing block 0x00000025 through 0x00000025.
    Target:Writing header and image data to Block 0x00000025, Page 0x00000000
    Target:Erasing block 0x00000026 through 0x00000026.
    Target:Writing header and image data to Block 0x00000026, Page 0x00000000
    Target:Erasing block 0x00000027 through 0x00000027.
    Target:Writing header and image data to Block 0x00000027, Page 0x00000000
    Target:Erasing block 0x00000028 through 0x00000028.
    Target:Writing header and image data to Block 0x00000028, Page 0x00000000
    Target:Erasing block 0x00000029 through 0x00000029.
    Target:Writing header and image data to Block 0x00000029, Page 0x00000000
    Target:Erasing block 0x0000002A through 0x0000002A.
    Target:Writing header and image data to Block 0x0000002A, Page 0x00000000
    Target:Erasing block 0x0000002B through 0x0000002B.
    Target:Writing header and image data to Block 0x0000002B, Page 0x00000000
    Target:Erasing block 0x0000002C through 0x0000002C.
    Target:Writing header and image data to Block 0x0000002C, Page 0x00000000
    Target:Erasing block 0x0000002D through 0x0000002D.
    Target:Writing header and image data to Block 0x0000002D, Page 0x00000000
    Target:Erasing block 0x0000002E through 0x0000002E.
    Target:Writing header and image data to Block 0x0000002E, Page 0x00000000
    Target:Erasing block 0x0000002F through 0x0000002F.
    Target:Writing header and image data to Block 0x0000002F, Page 0x00000000
    Target:Erasing block 0x00000030 through 0x00000030.
    Target:Writing header and image data to Block 0x00000030, Page 0x00000000
    Target:Erasing block 0x00000031 through 0x00000031.
    Target:Writing header and image data to Block 0x00000031, Page 0x00000000
    Target:Erasing block 0x00000032 through 0x00000032.
    Target:Writing header and image data to Block 0x00000032, Page 0x00000000
    Target:Protecting the entire NAND flash.
    Target:   DONE
    Target:   DONE

    Operation completed successfully.

  • in reply to jim liang12214
    TI__Mastermind 37340 points

    Jim,

    I beleive you are working with DM355 correct? If so, then I just replied back on your original post; I believe this thread was for DM365 and I would like to keep them separate just to avoid confusion...

  • in reply to Kevin Claycomb
    TI__Mastermind 37340 points

    Kevin Claycomb said:

    Have there been any updates to RBL in the V1.2 silicon?  I have a V1.1 TMX part on both of my DM365evms. 

    Kevin,

    Your suspicions are correct, MT29F16G08DAA  support was added in v 1.2 silicon.

  • in reply to Juan Gonzales
    Intellectual 420 points

    Juan Gonzales said:
    Your suspicions are correct, MT29F16G08DAA  support was added in v 1.2 silicon.

    Juan,

    Has this been confirmed by TI?  Since last I posted I have ordered another EVM.  This is a rev E evm has 1.2V silicon TMX320DM365BZCE.  I have not had any luck with the DAA part on this board either.  Are these thing documented anywhere for public release? I don't see anything in the 1.1 to 1.2 errata note with respect to RBL memory support mods.

    Thanks,

    Kevin

  • in reply to Kevin Claycomb
    TI__Mastermind 37340 points

    Kevin,

    Actually have an internal communication that states the DAA part is supported by silicon 1.2, but I do not see anything external available.  It was my understanding that the list of supported NAND device IDs in the ARM Subsystem UG listed not only the device IDs, but also the page sizes,... that RBL would recognize.

    I can certainly understand the confusion and since we have had a few requests on this topic, I am talking to our internal teams to see if we can improve our messaging and make it clearer what selection process our customers should follow.  I do not believe NAND IDs are enough, but need to dig further to get a simplified easy to understand process.  Thank you for your patience.