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TCI6636K2H: Checking/detecting any PRBS error on the RX side (RX PRBS Checker)

Nitish Gautam
Intellectual 690 points
Part Number: TCI6636K2H

Dear Support team,

I am working with our custom HW which contains TI custom processor TCI6636K2H. I am using MCSDK 3.1.3.6 for this purpose. I am more interested in knowing more about PRBS Checker section.

I am aware that TI has provided a in /diag/ section which contains example API for Serdes PRBS. I have used the provided example and modified based on our requirements. As there are 6 AIF2 Lanes in the TCI6636K2H processor. As per our custom hardware requirement we are more focused in PHY-A, 4 Lanes (B8) and PHY-A, 2 Lane (B4). For our application specific stuffs there,

3x lanes go to the FPGA

3x lane to the SFP

(A)  TRANSMIT TX PRBS pattern

As per the TI Provided example I have configure the Serdes_Example_PRBSTest(SERDES_AIF2_B8) and Serdes_Example_PRBSTest(SERDES_AIF2_B4) based on my requirements. I can verify Transmitter PRBS generator. WORKS

(B)    RECEIVE RX PRBS pattern

  1. I am more interested on PRBS verification (RX) side. Is there any way to verify what’s being transmitted is being received? For example, any counter or register on the DSP side to indicate that error has occurred? I know as per the manual http://www.ti.com/lit/ug/spruho3a/spruho3a.pdf BIST_CHK_ERRORS which should be non-zero (when error occurs) in my case its always 0.

 

2. How can check/detect the error on the serdes lane at the DSP end if the FPGA is transmitting with an injected error bit as per the above mentioned setup. Is there any error counter/ or any error register at DSP end which can be used to detect the error?

 

3. Also, while debugging I found that in the reserved section of the register as per the http://www.ti.com/lit/ug/spruho3a/spruho3a.pd manual. I have observed that when the setup is good i.e. TX PRBS pattern is initiated as per the (A), I can see the counter changing for all the lanes which are active and transmitting PRBS. Can you please let me know what is that counter mean?

PHY-A, 2 Lane (B4) à 0x02325FF8  (page 67 of the manual sub-system WIZ offset add: 0x1FF8)

PHY-A, 4 Lanes (B8) à 0x02327FF8  (page 71 of the manual sub-system WIZ offset add: 0x1FF8)

Looking forward to hear from you. Thanks

Kind Regards

Nitish