• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 99 subscribers
  • Views 490 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Compiler/66AK2H12: Any restriction to use ARM assembler command set "ldmfd" ?

Kz777
Expert 7895 points
Part Number: 66AK2H12
Other Parts Discussed in Thread: TEST2

Tool/software: TI C/C++ Compiler

Hi Champs,

We are using 66AK2H12. ARM assembler command.

Arm assembler command has "ldmfd" command.

<Question> 

Do we have any restriction to use this "ldmfd" command due to memory type or memory arrangement for multiple data "POP" operation ?

When we execute ldmfd sp!,{r3,r12,r15}, sometimes CPU is freezing.

However, when we change this  ldmfd sp!,{r3,r12,r15} execute address, this freezing situation was changed due to DDR3A/3B.

(Test1):logical address : 0x6000_xxxx and execute physical address:0x0_6000_xxxx(DDR3B) ->CPU freeze

(Test2):logical address : 0x6000_xxxx and execute physical address:0x8_0000_xxxx(DDR3A) ->No CPU freeze

(Test3):logical address : 0x8000_xxxx and execute physical address:0x8_0000_xxxx(DDR3A) ->CPU freeze

*When we PoP single data (i.e.ldmfd  sp!, {r3}、ldmfd  sp!, {r12}、ldmfd  sp!, {r15}) ,CPU didn't freeze at any condition.

It occur CPU freeze only multiple data POP case.

Regards,

Kz777 

  • 0
    TI__Guru**** 161600 points

    Hi,

    I wasn't able to find any restrictions in arm documentation:
    infocenter.arm.com/.../index.jsp
    infocenter.arm.com/.../index.jsp

    However, I know that there are some restrictions when it comes to arm core accessing DDR3B. For example in linux DDR3B is used for DSP and is not coherent with arm core and ARM core cannot access it (see: ), this may have something to do with what you experience.

    Also see the datasheet: Table8-1.DeviceMemoryMapSummaryfor 66AK2Hxx(continued) -> No IO coherencysupportedfor this region (se the KeyStone II ArchitectureARMCorePacUser's Guide).

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Expert 7895 points
    Hi Yordan,
    Sorry, for my late reply. We confirmed this phenomenon to customer.

    >(Test2):logical address : 0x6000_xxxx and execute physical address:0x8_0000_xxxx(DDR3A) ->No CPU freeze
    -This freeze issue is still occuring on the DDR3A also. We confirmed stack and heap place is DDR3A in this case.
    Do we have any restrict to use DDR3A (i.e, ICache or DCache setting or page table setting ?

    Regards,
    Kz777
  • 0 in reply to Kz777
    TI__Guru**** 161600 points
    Hi,

    No, as far as I know, there aren;t such restrictions. Let me consult the design team.

    Best Regards,
    Yordan
  • 0
    TI__Guru** 116170 points
    Kaz,

    There is no known restriction to using LDMFD instruction due to memory type or memory arrangement that we know of. You can check to see our exception handler for this device SVC_Handler and IRQ HAndler in the bare-metal CSL library for A15 uses this instructions without any issues.

    You can refer to the code provided here for the usage:
    pdk_k2hk_x_x_xx\packages\ti\csl\arch\a15\src\exceptionhandler_keystone.asm

    You may want to check on ARM forums if there is any limitation but there is nothing different in TI implementation of this core that will limit the instruction set.

    Regards,
    Rahul