Other Parts Discussed in Thread: ADS54J66, DAC37J82
I have an application with an ADC and DAC interfacing to an FPGA over JESD204B. I'm interested in replacing the FPGA with the 66AK2L06, but I'm trying to determine if my ADC/DAC sample clock rates and JESD204B data rates are compatible. Please correct me if anything I say below is incorrect.
I have an Analog Devices ADC (similar to the TI ADS54J66) which has 4 JESD204B lanes @ 15 Gbps. At the full 500 MSPS sample rate, I compute my JESD204B data rate as 10 Gbps, per ADC channel. With 4 ADC channels, the required 40 Gbps rate is too much for the 66AK2L06, which only supports 7.37 Gbps per lane (and at 4 lanes has a total supported rate of 29.48 Gbps). I can however decimate my data by 2 in the ADC prior to the JESD204B interface to reach a supported JESD204B line rate in the 66AK2L06. Is that correct? I.e., if I have 4 ADC channels at 250 MSPS, 16-bit real, will the 66AK2L06 support my JESD204B data rate needs?
My DAC is the TI DAC37J82 and has similar rate needs as the ADC above, so an answer above should help here.
As I was researching the JESD204B rates supported, I came across a posting from 2016 which stated that the only sample rates supported by the 66AK2L06 DFE are 245.76 or 368.64 MHz. I don't have a need for anything in the DFE besides the the JESD204B interface, but it sounded like the data was still required to be at one of these sample rates. Does the sample data from the ADC to the 66AK2L06 and sample data from the 66AK2L06 to the DAC need to be at one of these sample rates or is it more flexible than that?
Thanks.