Our customer wants to use SW leveling instead of HW leveling because they want to clarify the timing margin for each of their boards. In their experience, they know that DRAM has a timing margin variation and a high defect rate. SW leveling can know the timing margin while process which it is running, but HW leveling cannot.
There are some questions for SW leveling:
1) Do the EMIF_EXT_PHY_CONTROL_26 through EMIF_EXT_PHY_CONTROL_30 registers have to be configured?
These registers seem to be used only with HW leveling (read DQS gate training).
2) Does the EMIF_EXT_PHY_CONTROL_25 register have to be configured?
The EMIF_EXT_PHY_CONTROL_12 through EMIF_EXT_PHY_CONTROL_15 registers will be configured instead of the EMIF_EXT_PHY_CONTROL_25 register.
3) Does the REG_PHY_DQ_OFFSET_HI field in EMIF_EXT_PHY_CONTROL_24 register have to be configured?
The EMIF_EXT_PHY_CONTROL_16 register will be configured instead of the REG_PHY_DQ_OFFSET_HI field.
Best regards,
Daisuke
