We have designed PCB of SOM using AM335X for Ethernet communication.
We are doing signal integrity analysis on the board.But for SI analysis of the DDR bus ,we donot found any timing information in the datasheet.
We are using HyperLynx,it uses the DDR Wizard for which one of the requirement is the timing model of the DDR Controller.
Parameters required:
1. tCKAC (pre-launch delay, CK to Address and Command signals),
2 tCKCTL(pre-launch delay, CK to Control signals),
3 tCKDQS(Output delay or skew, CK output to DQS output),
4 tDQSDQ(pre-launch delay, DQS output to DQ and DM outputs)
and tDQDQS(Tolerable input skew between DQS and DQ).
So pl. provide the timing parameter listed above for analysis.
