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RTOS/66AK2H12: What is the most optimize way to use "Cache_invalidate"

Kz777
Expert 7895 points
Part Number: 66AK2H12
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi Champs,

We are evaluating K2H12.

<OS>

*RTOS base (we don't check detail version. However , this API use for all K2H RTOS version)

SYS/BIOS API<ti/sysbios/hal/Cache.h>

API name:Cache_inv.

 

*Send 20M data from ARM to DSP via external sharing memory.

So, we would like to invalidate "DSP" cache when DSP receive data.

However, our RTOS API prepare "cache_inv" API.  This "cache_inv" API need almost 10ms to invalidate all cache.

because, this API invalidate block level.

We would like to reduce this invalidate cache time.

We have cache_wbinvall() command also to invalidate all cache. However, we would like to avoid to use this command.

because, this "cache_wbinvall()" API　overwrite  latest DSP cache data that written by ARM.

Do you have any idea to reduce cache invalidate ?

Regards,

Kz777

 

  • 0
    TI__Guru* 95265 points
    Hi,

    The A15 writes 20MB data into the DDR memory, this is a shared memory region. The C66x DSP wants to use the data, so you have to cache_inv() to trash the cache line, then the DSP can read the data from physical memory. You can't use the cache_wbinvall(), it will write the data from cache into the memory. Is this the correct understanding of the usage case?

    Now, come to the cache_inv() API, this should have an address pointer and size you want to invalidate. In C66x the maximum L1D size is 32KB, you don't need to invalidate a size of 20MB, you just need invalidate 32KB. This should not take 10 ms.

    Regards, Eric