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Original question:

CCS/AM5718: Build XIP application

RTOS/AM5726: XIP for IPU/DSP

Alexander Aganichev
Intellectual 620 points
Part Number: AM5726

Tool/software: TI-RTOS

Hello!

It is not clear for me from the documentation/DRAx samples: is it possible to run IPU and DSP code from flash without copying them to DDR?

Is it possible with TI-RTOS based application on multiple cores?

  • 0
    Intellectual 620 points
    I understand that this will require custom SBL loader, but is it possible in theory?
  • 0 in reply to Alexander Aganichev
    TI__Guru** 116170 points
    Alexander,

    Yes in theory, this should be possible on AM572x using QSPI and GPMC NOR boot mode but we are not currently supporting this usecase in TI RTOS SDK. We are only supporting SD/MMC, eMMC and QSPI boot for this device where the application is copied into device memory.

    Currently, none of our HW platforms contains a parallel NOR interface . QSPI flash is supported but the driver and the usecases are primarily using configuration mode instead of direct mapped addressing mode.

    From device perspective, ROM bootloader on this device and the QSPI IP on this device supports execute in place. The SBL code in the RTOS SDK however relies on a out2rprc format that parses an ELF binary loads different section of code into device memory and brings slave cores DSP and IPU out of reset. This part of code will need to be modified such that the DSP is brought out of reset with entry point to a direct mapped address in GPMC address space or in QSPI address space.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Intellectual 620 points

    Thank you, Rahul!

    The what I want to achieve is the smallest possible boot time for IPU and DSP cores (preferrably no more than 300 ms from power up). We plan to use GPMC NOR flash.

    From the perspective of performance: will the running from GPMC NOR seriously affect IPU/DSP performance if most of the code can fit into the L2 cache?

  • 0 in reply to Alexander Aganichev
    TI__Guru** 116170 points
    Running code out of flash will have performance penalty even if cache is enabled for the region. If your code is not very large, I would try to leverage running a small bootloader that copies the code into DSP L2 memory or OCRAM memory so that you don`t have a performance penalty.

    We have automotive use cases where 200 KB image needs to boot on cores in < 50 ms and 1MB stack need to come up in 500 ms using QSPI 48 MHz that this device can meet so you will need to plan based on size of the firmware that you load. Parallel NOR should certainly be faster compared to QSPI NOR flash. If your motivation is fast boot and not creating a DDRless system then I would try to boot the slave core images on to onchip or DDR memory instead of trying to run it of flash.

    To be frank, the usecase that you are describing (XIP for slave cores ) has not been extensively tested at our end as this is an extremely rare use case to run slave core code of the flash so this would need some testing at your end to finalize the SW design.