66AK2H12: DDR3 Impedance Control Register 0

Kz777

Expert 7895 points

Part Number: 66AK2H12

Hi Champs,

We refer "spru7c" that is DDR3 user guide.
This TRM explain ZQnCR0 (n=0 to 3)

We have ZQnCR1、ZQnSR0、ZQnSR1 register.

However, I don't un clrear this "n" meaning. Could you please tell us this "n" definition ?

Regards,

Kz777

over 6 years ago

0 Yordan Kovachev over 6 years ago

TI__Guru**** 161600 points

Hi,

The "n" describes the number of PVT compensation pins for the DDR3 Controller. Since these documents are common for all devices of the Keystone family, you can check specific device datasheet to see how many PVT compensation pins are present for the device you use.

Best Regards,
Yordan

0 Kz777 over 6 years ago in reply to Yordan Kovachev

TI__Expert 7895 points

Hi , Thanks for your reply.
I checked K2H12 data sheet . This ptv compensation pins is each of 3 pins at DDR3A and DDR3B. (Total 6pins).
www.ti.com/.../66ak2h12.pdf (page19).

However, this "n" is maximum 0-3. (total:4) . So, We wonder this number is difference.
Could you please correct me if I miss understand it ?

Regards,
Kz777

0 Yordan Kovachev over 6 years ago in reply to Kz777

TI__Guru**** 161600 points

Hi,

As I said, the user guide is a common document including ALL K2H, K2E, K2L, K2K and so on devices. This is why the "n" varies between datasheets & differs from the User Guide.

Best Regards,
Yordan

0 Kz777 over 6 years ago in reply to Yordan Kovachev

TI__Expert 7895 points

HI, So, this "n" max number is 4. So, if K2H12 is each of 3 between DDR3A and DDR3B (Total=6), This "n" =3 and is it control DDR3A and DDR3B at same time ? 0,1,2 is for DDR3A1,2,3 and DDR3B1,2,3
This point didn't mention at data sheet.

0 Yordan Kovachev over 6 years ago in reply to Kz777

TI__Guru**** 161600 points

The pins are:
For DDR3A:
DDR3ARZQ0
DDR3ARZQ1
DDR3ARZQ2
For DDR3B
DDR3BRZQ0
DDR3BRZQ1
DDR3BRZQ2

So n = 0,1,2 for 66AK2H12 devices. See Table 4-4. Terminal Functions — By Signal Name.

Best Regards,
Yordan

0 Kz777 over 6 years ago in reply to Yordan Kovachev

TI__Expert 7895 points

Thanks. we understand it.

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66AK2H12: DDR3 Impedance Control Register 0