Hi,
The skew requirement value (DDR3 interval (A3 skew) at fly-by) of the CK and ADDR lines which is described in the datasheet of AM5728 by the wiring with DDR3 is stipulated as follows.
MAX: 6 ps
Table 8-12. CK and ADDR_CTRL Routing Specification
Converting to wiring length, it becomes about 0.7mm, which makes it very difficult to design the pattern.
Actually, how much can it tolerate?
Does this skew requirement value follow the DDR3 pattern design of AM572x IDK?
Best Regards,
Shigehiro Tsuda