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AM5728: DDR3 design layout

Part Number: AM5728

Hi,

The skew requirement value (DDR3 interval (A3 skew) at fly-by) of the CK and ADDR lines which is described in the datasheet of AM5728 by the wiring with DDR3 is stipulated as follows.
MAX: 6 ps
Table 8-12. CK and ADDR_CTRL Routing Specification

Converting to wiring length, it becomes about 0.7mm, which makes it very difficult to design the pattern.
Actually, how much can it tolerate?

Does this skew requirement value follow the DDR3 pattern design of AM572x IDK?

Best Regards,
Shigehiro Tsuda

  • Hi,

    Please see Note 1 below the table:

    "Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation."

    As for EVM designs, datasheet design requirements always have precedence over them.
  • Hi Biser,

    Thank you for quick reply.
    Does AM572x EVM or IDK have information on how many values ​​this value designs?
    Please explain why you decided that it is designed to be less than 6ps.

    Best Regards,
    Shigehiro Tsuda

  • Hi Shigehiro, I'm sorry but i don't understand the wording in your question. As Biser said, the datasheet guidelines should be followed, and if you need to deviate from those guidelines, signal integrity analysis should be performed.
    Most of the TI boards were designed before the datasheet guidelines were finalized, so you may see some minor violations in the board layout.

    Regards,
    James
  • Hi James,

    Thank you for quick reply.

    By your answer, I understood the following.

    When deviating from the layout rule of the data sheet, signal integrity analysis is required.
    Since the evaluation board is made before the layout rule of the data sheet is decided, it may deviate from it.

    Best Regards,
    Shigehiro Tsuda