AM4377: Trigger ADC1 Sampling with DMTimer

Please post what software and which version you are using.

The IDE is Code Composer Studio 8.3.0

For the Firmware I use TI RTOS: SYS/BIOS Version 6.73.00.12, am437x SDK Version 5.01.00.11 and PDK Version 1.0.12.

The XDCtools Version is 3.50.8.24

Based on your original post, it sounds like you may be trying to configure the ADC to perform a continuous sequence of measurements which begins with a hardware event. If that is the case, I'm not sure the ADC supports this function. This is based on the following description found in the "Software- or Hardware-Enabled Steps" section of the AM4377 TRM.

This hardware event will only schedule one complete sequence, even for continuous mode. If HW Enabled steps need to be executed again, a new hardware event must be generated after the previously triggered sequence has completed.

I'm not able to answer questions related to software configuration. I will need to find someone from our software team to help if you think your issue is related to software configuration.

Regards,
Paul

 

From my understanding the HW_SYNC_CONTINUOUS just means that the step is not disabled once it was executed so it is part of the sequence every time the hardware event occurs. Am I right?

And this is what I want. The sequence shall start every time the DMtimer has an overflow. 

Refering to the AM437x Technical Reference Manual this should be possible by chosing the TIMER5 pointr_pend as ext_hw_event by setting ADC1_EVTCAPT to 2 (Figure 12-1).

Figure 19-3 shows that the pointr_pend of the DMTIMER is connected to the ADC EVTCAPT (only ADC0 is mentioned in this figure). 

What I don't know is: Is there some additional routing/muxing necessary to "connect" pointr_pend of DMTimer5 to the ADC1 EVTCAPT mux? Do I need to configure something to set the pointr_pend on an event? For now I just enabled the Interrupt for the timer overflow.

Thanks

Sebastian

The FSM Sequencer diagram (Figure 12-2) indicates the step enable bit associated with a step is reset when the step is configured for one-shot mode, which seems to indicate the step enable bit associated with a step is not reset when configured for continuous mode. So I agree, this should be how the FSM works. However, the statement “This hardware event will only schedule one complete sequence, even for continuous mode” seems to contradict this expectation. Maybe this statement is simply try to tell the user the sequence is stopped when the ADC is disabled and a new hardware trigger will be needed once the ADC has been re-enabled. I will need to discuss this with someone from the design team and ask them to confirm how the FSM operates.

 

The POINTER_PEND signal output from DMTimer5 should be connected to the ARM interrupt input number 125 and the ADC1_EVTCAPT multiplexer input number 2. So I agree you should configure this register to select input 2 of the ADC1_EVTCAPT multiplexer.

 

Some of the AM437x TRM content originated from the previous AM335x device which only implemented a single ADC. There is a good chance Figure 9-3 was not updated when the second ADC was added to AM437x.

 

The ADC1_EVTCAPT bits need to be configured to select input 2 of the ADC1_EVTCAPT multiplexer.

The HW_EVT_MAPPING bit needs to be configured to select hardware event input mode.

The MODE bits need to be configured to select Hardware Synchronized, Continuous.

 

Regards,

Paul

Indeed I didn't set the HW_EVT_MAPPING. But anyways it is not working.

My current Configuration for the ADC:

- The ADC1 EVT_CAPT mux is set to 2:  HWREG(SOC_CONTROL_MODULE_REG + CTRL_MAG_EVT_CAPT /*CTRL_ADC1_EVT_CAPT*/) = 0x2U; //select DMTimer5

- The HW_EVT_MAPPING is set to 1: HWREG(adc1_base + ADC0_CTRL) = 0x142; // preamp bypass, put step id in adc results, set HW_EVT_MAPPING to 1 for ext_hw_evt

- The steps are HW_SYNC_CONTINUOUS (I tried ONE_SHOT, too) and enabled: 

HWREG(adc1_base + ADC0_STEPCONFIG(chan)) =

((ADC0_STEPCONFIG_AVERAGING_SAMPLESAVG_2 << ADC0_STEPCONFIG_AVERAGING_SHIFT) |
(ADC0_STEPCONFIG_FIFO_SELECT_0 << ADC0_STEPCONFIG_FIFO_SELECT_SHIFT) |
(3 << ADC0_TS_CHARGE_STEPCONFIG_SEL_RFP_SWC_SHIFT) | /* VREFP: 111 = VREFP */
(3 << ADC0_TS_CHARGE_STEPCONFIG_SEL_RFM_SWC_SHIFT) | /* VREFN: 11 = VREFN */
(ADC0_STEPCONFIG_MODE_HW_SYNC_CONTINUOUS << ADC0_STEPCONFIG_MODE_SHIFT) |
(0 << ADC0_STEPCONFIG_DIFF_CNTRL_SHIFT) |
((ain_seq[chan]) << ADC0_TS_CHARGE_STEPCONFIG_SEL_INP_SWC_SHIFT) |
((8) << ADC0_TS_CHARGE_STEPCONFIG_SEL_INM_SWM_SHIFT)); /* INM: 1000 = VREFN */

HWREG(adc1_base + ADC0_STEPEN) = ADC0_STEPEN_STEP1_MASK | ADC0_STEPEN_STEP2_MASK | ADC0_STEPEN_STEP3_MASK | ADC0_STEPEN_STEP4_MASK | ADC0_STEPEN_STEP5_MASK | ADC0_STEPEN_STEP6_MASK;

The Configuration for the DMTimer5:

- DMTimer Interrupt is cleared: DMTIMERIntrClear(DMTimer_base, 0x7U /*all interrupts*/);

- DMTimer Interrupt for Over flow event is enabled: DMTIMERIntrEnable(DMTimer_base, DMTIMER_INTR_MASK_OVF);

As I said, I checked that the timer counts and hardware interrupts are working.

Something still seems to be missing.

The functional description provided in the TRM was created based on several discussions with the original designer on operation of the FSM. I remember including the statement “This hardware event will only schedule one complete sequence, even for continuous mode” based on some input from him several years ago. However, I may have taken one of his comments out of context and misrepresented it with this statement. Unfortunately he no longer works for TI and we must look at the design to understand how it works.

 

I had someone look at the state machine design and they confirmed the respective step enable bit is only reset by the FSM when the step is configured for one-shot mode. So any steps configured for continuous mode should be repeated each pass through the sequencer. This sequence should continue until software disables the ADC.

 

The original designer may have wanted me to say a new hardware event is required to restart the sequence if software ever disables the ADC and re-enabled later.

 

It is not clear to me why the sequence doesn’t begin with a hardware event. What are you using as an indicator to determine the ADC never sees a hardware event? Have you checked the value of FIFOxCOUNT before and after the timer rollover to see if the FIFO pointer was incremented?

If you are absolutely convinced the ADC never sees the hardware event, you may need to create a interrupt service routine to service ARM interrupt TINT5 (#125) to confirm the timer is properly configured to create a transition on its pointr_pend output. However, I think you may have already checked this.

 

Regards,

Paul

Another suggestion which may help confirm the ADC is configured properly, is to try using the external ADC trigger input if your hardware platform supports this option. For example, you may be able to use a GPIO or export the timer event to one of the PWM outputs and looping it back to the ADC external trigger input.

Regards,
Paul

Have you made any progress?

I'm going to close this thread in a couple of days if I do not hear from you.

Regards,
Paul