How to write a BT.656 encoder driever for BT.656 display

BT.656 digital video output has been validated in hardware but this interface is currently not supported by our software.  In particular, due to lack of a hardware daughter card, the necessary code was not added to the encoder manager section of our Linux driver code; therefore, the first thing you would need to do is add proper support for the encoder part you choose to connect to the DM355 video output interface.

FYI, the driver file can be found under

.../ti-davinci/drivers/media/video/davinci

As you will notice, there are some supporting functions already built into the driver, but some work still needs to be done depending on the encoder part you choose.

Thanks for your reply. According to Chapter 2.2.2 in spruf72-Video Process Back End document, I did the setting as below:

/* Reset video encoder module */
 dispc_reg_out(VENC_VMOD, 0);
 
 /* Clear composite mode register */
 dispc_reg_out(VENC_CVBS, 0);
 
  /* Set VIDCTL to select VCLKE = 1,
    VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 , YCSWAP = 0*/
 dispc_reg_merge(VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
   VENC_VIDCTL_VCLKE);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
   VENC_VIDCTL_VCLKZ);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
   VENC_VIDCTL_SYDIR);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
   VENC_VIDCTL_YCDIR);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCSWAP_SHIFT,
   VENC_VIDCTL_YCSWAP);
 dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_DOMD_SHIFT,
   VENC_VIDCTL_DOMD);

 davinci_enc_set_display_timing(mode_info);
   
 /* Configure VMOD.*/
 dispc_reg_out(VENC_VMOD, 0x1201);
 /* Set REC656 Mode */
 dispc_reg_out(VENC_YCCCTL, 0x1);

Unfortunately there is no BT656 output. Can you kindly help me to check these settings?

It sounds like you have most of the settings correct, one thing to take a look at would be your PINMUX register settings to ensure that the VPBE video bus is properly pinned out. Do you get a pixel clock output when you run with this configuration?

What you have so far looks good, but you still need a few more registers; Like Bernie suggested, you need to worry about the pinmux registers, in particular PINMUX1 register.  Additionally, you also need a few more VPBE registers such as LCDOUT register to enable digital video output and VPSS CLKCTRL register to eanble output clock since you are configuring DM355 part as master.

When I add one setting dispc_reg_out(VENC_VDPRO, 0x0903); //CBMD = 1,Color bar output

The color bar can see. When try to play one *.mpeg4 file, still no picture appear. 

Color bars are generated internally in OSD hardware (as opposed to being read from DDR2), hence the fact that you can get color bars suggests that VPBE registers are mostly configured correctly and that the problem may be with the origin of the frame buffer. 

Can you verify that valid DDR2 window addresses are programmed into corresponding registers?

VIDWIN0ADL
VIDWIN1ADL
VIDWINADH
OSDWIN0ADL
OSDWIN1ADL
OSDWINADH 

I had another customer recently that after modifying the FBDEV driver, was not programming the addresses above correctly (he had all 0s) and was experiencing similar behavior.

Today, mpeg4 file can be appeared at last! But only appear half of the screen and abnormal color. Can you give me some hint? Thnak you very much!

By the way, when seting color bar output, it can be appeared the whole screen and correct color.

Half screen may be due to interlaced versus progressive setting.

Color bars are generated correctly regardless of progressive vs Interlaced settings.

A picture is worth 1000 words, for issues like this posting a picture of your video output can help to get more accurate suggestions, you can attach files to your profile on the forum to share such images. With the image we could easily see what you mean by abnormal color (probably some color space discrepancy) and only appearing on half of the screen (i.e. is it stretched or cropped, vertical halves or horizontal halves, etc.).

The picture size appeared normally at last after setting OSDCLK0.OCPW = 1 and OSCCLK1.OCPT = 2. These settings for interlace signal. Original I made a mistake to set these two registers as 0,1 for progressive signal.

Thanks for Juan giving so much good suggestion.

Now the size is normal, but the color seems some incorrect. This still need to fine tune.

If you can make out the image, but the colors are off, this can be due to

1) Color space conversion; for example, OSD window in VPBE can be configured to accept either RGB or YCbCr data.  If it is configured for RGB, but the data being read from DDR2 by OSD window is not in that pixel format, then you will see odd colors.

2) DM355 has the ability to swap Cb and Cr components of YCbCr piixel format (to provide greater compatibility with external video parts); if the display device expects these components in a different order than the DM355 is configured to output, this could also cause strange colors.

3) truncating pixel sizes can also have this effect; for example, hardware is configured to output 16-bit pixels, but only 10 bits (or pins) are connected to display device.

There might be other reasons, but this is all I can think of for now.  If the above does not help, sending as a picture as Bernie suggested, may allow us to give you additional advice.

Hi Juan & Bernie,

I have tried to attach the pictures but failed. I'm not sure how to fill the Image URL address.

Can I send these pictures to your mailbox?

I modified OSDWIN0MD.BMP0MD as 0(Bitmap), 1(RGB565, current setting), 3(YCbYCr). still no correct color.

Use 54200 signal generator output NTSC colorbar signal to TVP5146 in dm355 evaluation board.

You can

1) Attach file via options tab in your message reply

2) Upload file(s) via your profile page (as Bernie suggested above)

3) Send us an e-mail via your profile page

Ir order for the information to be helpful to others in the community, the first two are preferred.

Hi Juan & Bernie,

My rpofile has been updated. The picture is very blur. It seemed that there is no red color.

By the way, my platform is one mini projector. The fron end is used DPP1500.

Updated: Some pink color on the picture is caused by OSD menu. When removeing the OSD menu, the color bar seems normal but there still serious flicker on gray bar. 

smilejx,

The picture is a bit small, but seeing it along your explanation above brings a question to mind.

You suggest that when you remove OSD, color bar seems normal; does this mean that red shows up as you would expect? 

If colors are only distorted when OSD window is enabled, then this is likely not a color space conversion issue; I want to say this is due to transparency setting for OSD window, but I do not believe this would be accurate either. 

The flickering is likely due to video timing data not being sent at the right rate.  I am wondering what your output pixel clock (CVLK) is on an oscilloscope.

Juan Gonzales said:

1) Attach file via options tab in your message reply

Unfortunately attaching to a post directly is not possible for normal users, so if you cannot find the option to attach to your post in the options tab you are not missing anything, it is not there purposely. 

smilexj said:

My rpofile has been updated. The picture is very blur. It seemed that there is no red color.

I do see the picture as your avatar but that is a bit too small to make out much. It looks like the blue red and magenta are correct, though the green and cyan seem to be blurred and there looks to be a second smaller magenta bar around where yellow should be, though this could just be an artifact of the tiny image. If the forum is giving you trouble posting an image you could try to use a more generic image hosting service like http://imageshack.us/.

Juan & Bernie,

Thanks for your help again! Now the color and size of the picture appeares correct by refixed the data line connecting. VCLK is 27MHz on oscillograph.

This is great news.  Let us know if there is anything else we can assist you with going forward.

smilexj said:

Now the color and size of the picture appeares correct by refixed the data line connecting.

I am glad to hear it is working, does this mean that it was a hardware connection issue (swapped data lines or noise) that was causing the distortion?

I was reading this post.  I have the same question for the 6446.  I tried to post to the 6446 listing, but couldn't, so I'm posting it here (my apologies).

I've set what I thought was correct, but I'm not getting a good AV header.  Tends to be FF 0 80, rather than FF 0 0 80, and similar inconsistencies.

I have a 54Meg clock on VPBECLK, and I want the data to come out on VOUT[7..0] as BT-656 data, NTSC timing.

With the settings below, it looks like VCLK is being produced at 54MHz.

Here are my register settings. If it's not listed, it's not changed from the Power-Up default value.

//PCR.CLK_OFF (bit 0) Normal (0) vs Clocks-disabled (1). Set to 0 to change other registers.

//VPSS_CLKCTL.VENCLKEN - (bit 3) set to '1' to enable ENC_CLK
//VPSS_CLKCTL. MUXSEL - (bits 1:0) need to be set to '2', VPBECLK mode

//VMOD.VDMD (bits 15:12) := 1.
//VMOD.ITLCL (bit 11) := 0
//VMOD.ITLC (bit 10) := 1
//VMOD.TVTYP (bits 7:6) := 0 for NTSC, 1 for PAL. Choosing NTSC
//VMOD.VMD (bit 4) := 0. use NTSC/PAL timing.
//VMOD.VENC (bit 0) := 0 0 for disable or configuration, 1 for enable

// Set to 1 after final configuration to start encoder.

//YCCTL.CHM (bit 4) := 1 ? Maybe 0?
//YCCTL.YCP (bits 3:2) := 0
//YCCTL.R656 (bit-0 ) := 1

//RGBCTL.DFLTS (bits 9:8) := 0 (disable RGB function)

//VIDCTL.VCLKE (bit 13) := 1
//VIDCTL.VCLKZ (bit 12) := 0 Enable VCLK driver. Needs to be changed from default setting
//VIDCTL.VDMD := 0. Page 35 of SPRUE37 calls this field & name out, but the field doesn't exist in listing.

//I think this is actually DOMD (bits 5:4) := 0.

//HSTART and VSTART still have their default values of 0

I couldn't tell from SPRUE37 if H_VALID and V_VALID needed to be set, or if they were given values when you select BT-656 mode.

At the moment, I have set them with non-zero values. If I need to set them, what should their values be?

//VIDWIN0ADR is set to the start of the data, at hex-8000_0000, which I've initialized to something obvious, 1 2 3 4 5 etc.

and final step:

// Enable the Video Encoder

//VMOD.VENC (bit 0) := 0 for disable, 1 for enable.

An extra question: If I just want to send a single frame (not interlaced), how do I stop the Vid Encoder from sending a second frame?

Thanks in advance for help,

JTL

Hi smilexj

     I now write BT656 driver of BT656 display on DM355.

     at present I add one setting dispc_reg_out(VENC_VDPRO, 0x0903); The color bar can see,but play *.avi file,no picture appear on the screen.

     whether you can tell me how to modify codes to realize to display *avi on the screen.Thank for you!