Hi,everyone
There are some encoders in DM355 for SDTV and LCD panel.
According to Chapter 2.2.2 in spruf72-Video Process Back End document; I did the setting as below:
.../ti-davinci/drivers/media/video/davinci/davinci_platform.c
/*setting PAL mode*/
static void davinci_enc_set_pal(struct vid_enc_mode_info *mode_info)
{
/*Initialize the VPSS Clock control register*/
davinci_writel(0x18,SYS_VPSS_CLKCTL);
davinci_writel(0,(DM644X_VPBE_REG_BASE + VPBE_PCR));
/* Reset video encoder module */
dispc_reg_out(VENC_VMOD, 0);
/* Clear composite mode register */
dispc_reg_out(VENC_CVBS, 0);
/* Set VIDCTL to select VCLKE = 1,
VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 , YCSWAP = 0*/
dispc_reg_out(VENC_VIDCTL, 0x2000);
davinci_enc_set_display_timing(mode_info);
/* Configure VMOD.*/
dispc_reg_out(VENC_VMOD, 0x1201);
/* Set REC656 Mode */
dispc_reg_out(VENC_YCCCTL, 0x1);
dispc_reg_out(VENC_VDPRO, 0x0903);
dispc_reg_out(VENC_OSDCLK0, 1);
dispc_reg_out(VENC_OSDCLK1, 2);
if (cpu_is_davinci_dm355()) {
davinci_writel(mode_info->left_margin,
(DM355_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM355_OSD_REG_BASE + OSD_BASEPY));
} else {
davinci_writel(mode_info->left_margin,
(DM644X_OSD_REG_BASE + OSD_BASEPX));
davinci_writel(mode_info->upper_margin,
(DM644X_OSD_REG_BASE + OSD_BASEPY));
}
dispc_reg_merge(VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
}
VCLK is 27MHz on oscillograph, but YOUT0~YOUT7 is not signal,there is no BT656 encoder for BT656 display.Can someone give me some hint how to implement this driver? The sample code for BT656 encoder is appreciated.
