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DM365 ADC clock configuration (BUG?)

Hi,

while writing a driver for DM365's ADC I've noticed a strangeness that seems a bug but I'd like to confirm with TI. Please check file "arch/arm/mach-davinci/clock.c", where struct clk "davinci_dm365_clks" is defined. The entry for ADC clock is:

    {
        .name = "ADCIF_CLK",
        .rate = &commonrate,
        .lpsc = DAVINCI_DM365_LPSC_ADCIF,
    },

The "rate" value is set to "commonrate", that is 121.5Mhz. But if we check "sprs457" document, section 3.3.1, figure 3-2 there is a picture where ADC device is connected to "Oscillator". This means that the correct entry for ADC should have rate "fixedrate" instead:

    {
        .name = "ADCIF_CLK",
        .rate = &fixedrate,
        .lpsc = DAVINCI_DM365_LPSC_ADCIF,
    },

In fact UART0, UART1 I2C PWM USB entries all use "fixedrate" and in the picture they are connected to "Oscillator".

So what's the correct configuration?