TMS320C6748: SPI/I2C slave boot supported max clock

Tony Tang

Part Number: TMS320C6748

What is the supported max interface clock of C6748 SPI/I2C slave boot?

I think as long as the clock less than the min cycle time in data sheet is OK for the interface, but I am not sure whether ROM bootloader can support the throughput? if need to insert delay from host side, how to determine the delay time?

over 6 years ago

0 Cvetolin Shulev-XID over 6 years ago

TI__Guru 65405 points

Hi Tony,

The max SPI clock supported for master mode is 50 MHz as per the data sheet Tab 6-68. This is true for 1.2 - 1.3V operating voltage.
The max I2C clock in fast mode is 400 KHz and 100 KHz in standard mode (datasheet Tab 6-85).
www.ti.com/.../tms320c6748.pdf

Regards,
Tsvetolin Shulev

0 Tony Tang over 6 years ago in reply to Cvetolin Shulev-XID

TI__Mastermind 28922 points

Shulev,

I am asking SPI/I2C slave boot mode.

and I am asking the bootloader supported throughput. I know well the max interface clock from datasheet. in Slave SPI mode, C6748 support 25MHz maximum, but can bootloader accept data continually without delay between word in 25MHz SPI_CLK?

0 Rahul Prabhu over 6 years ago in reply to Tony Tang

TI__Guru** 116170 points

Tony,

The bootloader on C6748 doesn`t use dma implementation so getting to theoretical max should not be the expectation when booting. From previous user experience, we have seen usage of up to 10-12 Mhz on the SPI in slave mode.

I will share some data offline in terms of what users have implemented in the past to help your customer make the right decision choices.

Regards,
Rahul

PS: If the back ground for this is boot times we only provide estimates for master boot modes :
processors.wiki.ti.com/.../OMAP-L138_Boot_Benchmarks

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TMS320C6748: SPI/I2C slave boot supported max clock