RTOS/TIDEP0025: 33.3kHz PWM frequency in TIDEP0025 demo

It appears like the initialization of the PWM signals may have something to do with this. I made a change on my local setup to only enable the PWM clocks at the end of the PWM initialization and it corrected the issue for me. Can you try to following change and let me know if it works for you as well?

Create the following function in the foc_pwm.c file:

void CtrlPwmssTimebaseClkDisable(void)
{
     /*CTRL_PWMSS - PWM3 syncin from PIN (eHRPWM3), timebase clock disable for all*/
     HWREG(SOC_CONTROL_MODULE_REG + CTRL_PWMSS) = CTRL_PWMSS_PWM_SYNCSEL_MASK;
}

Call that function at the BEGINNING of the Drv_PWM_Init() function (in the foc_pwm.c file) in order to disable the clock to the PWMs while the initiializations is happening.

Now, at the END of the Drv_PWM_Init() function (in the foc_pwm.c file) you need to add a barrier instruction (to make sure all of the configurations have landed in the registers) and then re-enable all of the PWM clocks at the exact same time:

HW_SYNC_BARRIER();

CtrlPwmssTimebaseClkEnable();

After all of these changes the function should look something like this:

void Drv_PWM_Init(PWMGEN *p)
{
    Int32 Tm;
    Tm = (Int32)p->PeriodMax;
    Int16 MPeriod;
    Int32 Tmp;

    CtrlPwmssTimebaseClkDisable();

    ...
    Initialization of PWMs
    ...

    HW_SYNC_BARRIER();

    CtrlPwmssTimebaseClkEnable();
}

This solved the issue for me both when running the CPU at 300MHz and when trying to run the PWM cycle at 25kHz (with the CPU at 600MHz).

Let me know if this fixes your issue.

Jason Reeder

Hi,

Can you confirm which versions of the Industrial Drives package that you are using? I've found that version 01.00.02.03 has an optimization when writing the three PWM values that the 01.00.02.00 version does NOT have. If you are using version 01.00.02.00 you need to replace the three calls to the CSL_epwmCounterComparatorCfg() at the bottom of your Drv_PWM_Update() function (in the foc_pwm.c file) with the following code:

    HWREGH(SOC_PWMSS3_REG + PWMSS_EPWM_OFFSET + PWMSS_EPWM_CMPA) = (uint16_t)p->PWM1out;
    HWREGH(SOC_PWMSS4_REG + PWMSS_EPWM_OFFSET + PWMSS_EPWM_CMPA) = (uint16_t)p->PWM2out;
    HWREGH(SOC_PWMSS5_REG + PWMSS_EPWM_OFFSET + PWMSS_EPWM_CMPA) = (uint16_t)p->PWM3out;

    HW_SYNC_BARRIER();

Once I did this in my CiA402 motor control setup, my FOC loop timing (at 300MHz A9 frequency) changed from ~11.7us to ~8.8us.

I think if you have the following 3 changes you should be able to achieve 33kHz at either 300MHz or 600MHz (using TIDEP0025 demo (EnDat and CiA402)):

1. The Drv_PWM_Init() function update already listed previously in this E2E thread (to sync the PWMs at the beginning of the demo)
2. The Drv_PWM_Update() function change mentioned in this post (to reduce timings by nearly 3us at 300MHz)
3. Change the iep_endat_start offset to (PWM_PERIOD >> 1) - 400. This will move the EnDat position capture to the middle of the PWM cycle and will ensure that the EnDat trigger occurs at 25kHz and 33kHz PWM cycle times.
   1. To achieve this, make the iep_endat_start line in the foc.c file look like the below (change 20000 to 400):
      1.     p_mem_foc_params->iep_endat_start = (PWM_PERIOD >> 1) - 400;

Let me know if these three changes make your TIDEP0025 demo run correctly at 33kHz while the Arm is running at 300MHz.

Jason Reeder