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AM5K2E02: Sysboot pins

Jasvinder Marwaha
Prodigy 245 points
Part Number: AM5K2E02

Hi,

We are testing a custom PCB with a AM5K2E02 SOC.

We have observed that on boot the DEVSTAT register contains different values for the SYSBOOT pins than were expected. Intended 0's are always registered correctly as 0's. However some intended 1's register incorrectly as 0's. System operation appears to follow the DEVSTAT indicated values. For example, we have SYSBOOT[9] tied to 1.8V but this is always latched as a 0 in DEVSTAT[10].

All SYSBOOT pins are tracked and either have a 100K pull down to supplement the IPD or a 1K pull up to oppose the IPD. We also have a 47pF to ground for noise immunity.

We have verified the power sequence is correct.

We have observed that SYSBOOT pin values are stable during reset.

Are there any known reasons why the SYSBOOT would be latched incorrectly?

Are there any other ares of our design could cause this behaviour?

Thanks,

Jasvinder 

  • 0
    TI__Mastermind 46460 points

    Jasvinder,

    The Data Manual recommends use of a 20K resistor to complement an internal pull that is to the same value.  Also, timing analysis assumed minimal capacitance.  The 47pF capacitors are not recommended and not comprehended in the timing associated with these pins being used for BOOTMODE latching.  Can you test with the 100K resistors changed to 20K resistors and the capacitors removed?  This will eliminate these variations from the observed behavior.

    Do you see the same DEVSTAT value latched every time or does it vary?  Do all boards behave the same?  How many boards have you tested?  Please provide the expected BOOT Configuration pin strapping and the value latched.  Does it behave the same from a power-up start as from an emulator reset?

    Are these pins used only for BOOT configuration or do they route out for other use during runtime?  If so, how are you releasing them for BOOT latching when the device re-enters reset?

    Tom

  • 0 in reply to Tom Johnson 16214
    Prodigy 245 points
    Hi Tom,

    Thanks for this response.

    The DEVSTAT values were sometimes changing and the boards were behaving differently. We were able to determine this was due to a connection issue between the processor and the resistors which we have now resolved. Boot latching is now stable and as expected.

    The Pins were only used for boot configuration so had no need to be released. Thanks again for your response.

    Jasvinder