AM4376: CPSW memory usage when operating in EMAC only mode

Gunter, please find the response from our Design team below:

In a CPSW, each port has a FIFO RAM (including the HOST port).  The FIFO ram is unused for any port that is unused.  Every other RAM in the CPSW is used.

When looking at CPSW memories you need to understand the use of such memories for FIT rate purposes.

• The CPSW FIFO memories only store the packet and related info while it is in transit, the FIFO memories do not store any permanent control plane data. That is temporal failures while not in use have no effect.
• The CPSW ALE memories do store control plane data that determines the route of a packet, a bit hit at worst misroutes or drops a packet. Causing upper level protocols to enter recovery modes.

All CPSW modules support end-to-end protection, that is in all CPSW versions, the packet is protected while in the memory using a CRC.

That is while the packet is in memory, if the packet takes a bit hit, the packet will be sent with an error. In actuality the protection also cover a myriad of internal logic as well. The CRC ensures the end to end protection of packets which is a requirement of IEEE compliant bridges.

Also to note, the packets only live in memory for a very short time, and bit hits that hit the memory while not in use do not affect anything.