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RTOS/PROCESSOR-SDK-AM437X: Several questions about the ICSS EMAC LLD developers guide

user5371084
Expert 2215 points
Part Number: PROCESSOR-SDK-AM437X

Tool/software: TI-RTOS

Now I am researching the document "ICSS EMAC LLD developers guide"

I have several questions as follow:

1. in the Rx Data Path, when the received packets are copied from PRU to L3 Memory, PRU's then assert an interrupt to tell the Host about the presence of a packe. What mechanism does PRU adopt to avoid corruption and does not write over the memory till the packet is copied by the Host.

2. in the Tx Data Path, API ICSS_EmacTxPacketEnqueue which performs the actual task of copying data from DDR to L3 and signals the PRU to transmit the data. How to implement that the ARM host signals the PRU to transmit the data?

3. from this guide, I know PRU write its received pockets to the L3 OCMC RAM, and read sending pocket from the L3 OCMC RAM. does it read and write the L3 though the OCP Master port?

  • 0
    TI__Mastermind 43296 points
    zhuangbin,

    1. The buffer descriptor and queue descriptor do the memory management, see section 3.1.7 Buffer Descriptors, Queue Descriptors and Receive Context in the document ICSS_DUAL_EMAC_Firmware_Design_Guide.pdf under PDK packages\ti\drv\icss_emac\firmware\icss_dualemac\docs for details:
    Queue descriptor bit 32-39, busy_s, is just a single bit. The busy bit is set by the driver to indicate to the firmware that there is an ongoing copy, firmware does not use the memory during that time.

    2. You can refer to the section '3.1.9.1 Transmit Task design' - Transmit task scans the send queues to determine whether there is a frame to be transmitted. It first looks at the highest priority queue and if it is empty then only checks the lower priority queues. If all the send queues are empty then it returns to the scheduler.

    3. Yes.

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Expert 2215 points

    Yes, I need to research this information.

    Thank you.